LM3S1637 Datasheet, PDF (82/696 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

The Cortex-M3 Processor
2.5.3
2.5.4
Table 2-9. Interrupts (continued)
Vector Number
46
47
48
49
50
51
52
53-58
59
Interrupt Number (Bit
in Interrupt Registers)
30
31
32
33
34
35
36
37-42
43
Vector Address or
Offset
0x0000.00B8
0x0000.00BC
0x0000.00C0
0x0000.00C4
-
0x0000.00CC
0x0000.00D0
-
0x0000.00EC
Description
GPIO Port F
GPIO Port G
GPIO Port H
UART2
Reserved
Timer 3A
Timer 3B
Reserved
Hibernation Module
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 80. Figure 2-6 on page 83 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
82
June 18, 2012
Texas Instruments-Production Data