LM3S1637 Datasheet, PDF (631/696 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1637 Microcontroller
Table 19-5. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
VDDA
C6
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 645, regardless of system implementation.
VDDA
C7
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 645, regardless of system implementation.
PH1
I/O
TTL
GPIO port H bit 1.
C8
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
PH0
I/O
TTL
GPIO port H bit 0.
C9
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
C10
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
PB2
C11
I2C0SCL
I/O
TTL
GPIO port B bit 2.
I/O
OD
I²C module 0 clock.
PB3
C12
I2C0SDA
I/O
TTL
GPIO port B bit 3.
I/O
OD
I²C module 0 data.
D1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
D10
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D11
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
PB1
D12
CCP2
I/O
TTL
GPIO port B bit 1.
I/O
TTL
Capture/Compare/PWM 2.
E1
PD4
I/O
TTL
GPIO port D bit 4.
E2
PD5
I/O
TTL
GPIO port D bit 5.
LDO
E3
-
Power Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDD25 pins at the board level
in addition to the decoupling capacitor(s).
E10
VDD33
-
Power Positive supply for I/O and some logic.
E11
CMOD0
I
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
PB0
E12
CCP0
I/O
TTL
GPIO port B bit 0.
I/O
TTL
Capture/Compare/PWM 0.
PD7
I/O
TTL
GPIO port D bit 7.
F1
IDX0
I
TTL
QEI module 0 index.
PD6
I/O
TTL
GPIO port D bit 6.
F2
Fault
I
TTL
PWM Fault.
F3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
June 18, 2012
631
Texas Instruments-Production Data