LM3S1637 Datasheet, PDF (573/696 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1637 Microcontroller
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014
This register controls the global interrupt generation capabilities of the PWM module. The events
that can cause an interrupt are the fault input and the individual interrupts from the PWM generators.
PWM Interrupt Enable (PWMINTEN)
Base 0x4002.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
IntFault
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IntPWM2 IntPWM1 IntPWM0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:17
16
15:3
2
1
0
Name
reserved
IntFault
reserved
IntPWM2
IntPWM1
IntPWM0
Type
RO
R/W
RO
R/W
R/W
R/W
Reset
0x00
0
0x00
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Interrupt Enable
When set, an interrupt occurs when the fault input is asserted.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM2 Interrupt Enable
When set, an interrupt occurs when the PWM generator 2 block asserts
an interrupt.
PWM1 Interrupt Enable
When set, an interrupt occurs when the PWM generator 1 block asserts
an interrupt.
PWM0 Interrupt Enable
When set, an interrupt occurs when the PWM generator 0 block asserts
an interrupt.
June 18, 2012
573
Texas Instruments-Production Data