LM3S1637 Datasheet, PDF (11/696 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1637 Microcontroller
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 478
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 479
Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 479
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 480
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 481
Figure 14-1. I²C Block Diagram ............................................................................................. 510
Figure 14-2. I²C Bus Configuration ........................................................................................ 511
Figure 14-3. START and STOP Conditions ............................................................................. 511
Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 512
Figure 14-5. R/S Bit in First Byte ............................................................................................ 512
Figure 14-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 512
Figure 14-7. Master Single SEND .......................................................................................... 516
Figure 14-8. Master Single RECEIVE ..................................................................................... 517
Figure 14-9. Master Burst SEND ........................................................................................... 518
Figure 14-10. Master Burst RECEIVE ...................................................................................... 519
Figure 14-11. Master Burst RECEIVE after Burst SEND ............................................................ 520
Figure 14-12. Master Burst SEND after Burst RECEIVE ............................................................ 521
Figure 14-13. Slave Command Sequence ................................................................................ 522
Figure 15-1. Analog Comparator Module Block Diagram ......................................................... 546
Figure 15-2. Structure of Comparator Unit .............................................................................. 547
Figure 15-3. Comparator Internal Reference Structure ............................................................ 548
Figure 16-1. PWM Unit Diagram ............................................................................................ 559
Figure 16-2. PWM Module Block Diagram .............................................................................. 560
Figure 16-3. PWM Count-Down Mode .................................................................................... 562
Figure 16-4. PWM Count-Up/Down Mode .............................................................................. 562
Figure 16-5. PWM Generation Example In Count-Up/Down Mode ........................................... 563
Figure 16-6. PWM Dead-Band Generator ............................................................................... 563
Figure 17-1. QEI Block Diagram ............................................................................................ 598
Figure 17-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 600
Figure 18-1. 100-Pin LQFP Package Pin Diagram .................................................................. 615
Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 616
Figure 21-1. Load Conditions ................................................................................................ 648
Figure 21-2. JTAG Test Clock Input Timing ............................................................................. 651
Figure 21-3. JTAG Test Access Port (TAP) Timing .................................................................. 651
Figure 21-4. JTAG TRST Timing ............................................................................................ 651
Figure 21-5. External Reset Timing (RST) .............................................................................. 652
Figure 21-6. Power-On Reset Timing ..................................................................................... 652
Figure 21-7. Brown-Out Reset Timing .................................................................................... 653
Figure 21-8. Software Reset Timing ....................................................................................... 653
Figure 21-9. Watchdog Reset Timing ..................................................................................... 653
Figure 21-10. Hibernation Module Timing ................................................................................. 654
Figure 21-11. ADC Input Equivalency Diagram ......................................................................... 655
Figure 21-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 656
Figure 21-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 657
Figure 21-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 657
Figure 21-15. I²C Timing ......................................................................................................... 658
Figure D-1. Stellaris LM3S1637 100-Pin LQFP Package Dimensions ..................................... 688
June 18, 2012
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