LM3S1637 Datasheet, PDF (598/696 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Quadrature Encoder Interface (QEI)
Figure 17-1. QEI Block Diagram
Control & Status
QEICTL
QEISTAT
QEILOAD
Velocity Timer
QEITIME
PhA
PhB
IDX
Velocity
Predivider
clk
Quadrature
Encoder dir
Velocity Accumulator
QEICOUNT
QEISPEED
QEIMAXPOS
Position Integrator
QEIPOS
QEIINTEN
Interrupt Control
QEIRIS
QEIISC
Interrupt
17.2
Signal Description
Table 17-1 on page 598 and Table 17-2 on page 598 list the external signals of the QEI module and
describe the function of each. The QEI signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the
possible GPIO pin placements for these QEI signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 305) should be set to choose the QEI function. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 283.
Table 17-1. QEI Signals (100LQFP)
Pin Name
Pin Number Pin Type Buffer Type^a Description
IDX0
100
I
TTL
QEI module 0 index.
PhA0
25
I
TTL
QEI module 0 phase A.
PhB0
22
I
TTL
QEI module 0 phase B.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 17-2. QEI Signals (108BGA)
Pin Name
Pin Number Pin Type Buffer Type^a Description
IDX0
F1
I
TTL
QEI module 0 index.
PhA0
L1
I
TTL
QEI module 0 phase A.
PhB0
L2
I
TTL
QEI module 0 phase B.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
598
June 18, 2012
Texas Instruments-Production Data