LM3S1637 Datasheet, PDF(288/696 Page) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

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LM3S1637 Datasheet, PDF (288/696 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

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General-Purpose Input/Outputs (GPIOs)

Table 8-5. GPIO Signals (108BGA) (continued)

Pin Name

Pin Number Pin Type Buffer Typea Description

PB5

B7

I/O

TTL

GPIO port B bit 5.

PB6

A7

I/O

TTL

GPIO port B bit 6.

PB7

A8

I/O

TTL

GPIO port B bit 7.

PC0

A9

I/O

TTL

GPIO port C bit 0.

PC1

B9

I/O

TTL

GPIO port C bit 1.

PC2

B8

I/O

TTL

GPIO port C bit 2.

PC3

A10

I/O

TTL

GPIO port C bit 3.

PC4

L1

I/O

TTL

GPIO port C bit 4.

PC5

M1

I/O

TTL

GPIO port C bit 5.

PC6

M2

I/O

TTL

GPIO port C bit 6.

PC7

L2

I/O

TTL

GPIO port C bit 7.

PD0

G1

I/O

TTL

GPIO port D bit 0.

PD1

G2

I/O

TTL

GPIO port D bit 1.

PD2

H2

I/O

TTL

GPIO port D bit 2.

PD3

H1

I/O

TTL

GPIO port D bit 3.

PD4

E1

I/O

TTL

GPIO port D bit 4.

PD5

E2

I/O

TTL

GPIO port D bit 5.

PD6

F2

I/O

TTL

GPIO port D bit 6.

PD7

F1

I/O

TTL

GPIO port D bit 7.

PE0

A11

I/O

TTL

GPIO port E bit 0.

PE1

B12

I/O

TTL

GPIO port E bit 1.

PF0

M9

I/O

TTL

GPIO port F bit 0.

PF1

H12

I/O

TTL

GPIO port F bit 1.

PF2

J11

I/O

TTL

GPIO port F bit 2.

PF3

J12

I/O

TTL

GPIO port F bit 3.

PG0

K1

I/O

TTL

GPIO port G bit 0.

PG1

K2

I/O

TTL

GPIO port G bit 1.

PG2

J1

I/O

TTL

GPIO port G bit 2.

PH0

C9

I/O

TTL

GPIO port H bit 0.

PH1

C8

I/O

TTL

GPIO port H bit 1.

a. The TTL designation indicates the pin has TTL-compatible voltage levels.

8.2 Functional Description

Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,

and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).

The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,

GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both

groups of pins back to their default state.

While debugging systems where PB7 is being used as a GPIO, care must be taken to

ensure that a low value is not applied to the pin when the part is reset. Because PB7

reverts to the TRST function after reset, a Low value on the pin causes the JTAG

controller to be reset, resulting in a loss of JTAG communication.

288

June 18, 2012

Texas Instruments-Production Data

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