DS92LV3221_14 Datasheet, PDF (8/30 Pages) Texas Instruments – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3221, DS92LV3222
SNLS319C – OCTOBER 2009 – REVISED APRIL 2013
www.ti.com
SERIALIZER INPUT TIMING REQUIREMENTS FOR TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
t_CIP
TxCLKIN Period
t_CIH
TxCLKIN High Time
t_TCIL
TxCLKIN Low Time
t_CIT
TxCLKIN Transition Time
20 MHz – 50 MHz
20 MHz – 50 MHz
Figure 5
20 MHz – 50 MHz
Figure 4
20
0.45 x
t_CIP
0.45 x
t_CIP
0.5
t_JIT
TxCLKIN Jitter
Typ
t_CIP
0.5 x t_CIP
0.5 x t_CIP
Max
50
0.55 x
t_CIP
0.55 x
t_CIP
1.2
±100
Units
ns
ns
ns
ns
ps_P-P
SERIALIZER SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
t_LLHT
t_LHLT
t_STC
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
TxIN[31:0] Setup to TxCLKIN
No pre-emphasis
Figure 3
IOVDD = 1.71V to 1.89V
Figure 5
350
350
0
IOVDD = 3.135V to 3.465V
0
t_HTC
TxIN[31:0] Hold from TxCLKIN
IOVDD = 1.71V to 1.89V
IOVDD = 3.135V to 3.465V
2.5
2.25
t_PLD
Serializer PLL Lock Time
Figure 7
t_LZD
Data Output LOW to TRI-STATE
See ⁽¹⁾
Delay
t_HZD
Data Output TRI-STATE to HIGH
See ⁽¹⁾
Delay
4400 x
t_CIP
5
5000 x
t_CIP
10
5
10
t_SD
Serializer Propagation Delay - Latency f = 50 MHz, R_FB = H,
PRE = OFF,
Figure 6
4.5 t_CIP +
6.77
f = 50 MHz, R_FB = L,
PRE = OFF,
Figure 6
4.5 t_CIP + 4.5 t_CIP + 4.5 t_CIP +
5.63
7.09
9.29
f = 20 MHz, R_FB = H,
PRE = OFF,
4.5 t_CIP + 4.5 t_CIP + 4.5 t_CIP +
6.57
8.74
10.74
t_LVSKD
LVDS Output Skew
LVDS differential output channel-to-
channel skew
30
500
Λ_STXBW
Jitter Transfer Function -3 dB
Bandwidth
f = 50 MHz
Figure 13
2.8
δ_STX
Serializer Jitter Transfer Function
Peaking
f = 50 MHz
0.3
Units
ps
ps
ns
ns
ns
ns
ns
ns
ps
MHz
dB
(1) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
8
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