DS92LV3221_14 Datasheet, PDF (19/30 Pages) Texas Instruments – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3221, DS92LV3222
www.ti.com
SNLS319C – OCTOBER 2009 – REVISED APRIL 2013
TYPICAL APPLICATION CONNECTION
Figure 18 shows a typical application of the DS92LV3221 Serializer (SER). The differential outputs utilize 100nF
coupling capacitors to the serial lines. Bypass capacitors are placed near the power supply pins. A system GPO
(General Purpose Output) controls the PDB and BISTEN pins. In this application the R_FB (SER) pin is tied Low
to latch data on the falling edge of the TxCLKIN. In this application the link is short, therefore the VSEL pin is tied
LOW for the standard output swing level. The Pre-emphasis input utilizes a resistor to ground to set the amount
of pre-emphasis desired by the application.
Configuration pins for the typical application are shown for SER:
• PDB – Power Down Control Input – Connect to host or tie HIGH (always ON)
• BISTEN – Mode Input - tie LOW if BIST mode is not used, or connect to host
• VSEL – tie LOW for normal VOD (application dependant)
• PRE – Leave open if not required (have a R pad option on PCB)
• RSVD1 & RSVD2 – tie LOW
There are eight power pins for the device. These may be bussed together on a common 3.3V plane (3.3V
LVCMOS I/O interface). If 1.8V input swing level for parallel data and control pins are required, connect the
IOVDD pin to 1.8V. At a minimum, eight 0.1uF capacitors should be used for local bypassing.
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Product Folder Links: DS92LV3221 DS92LV3222