DS92LV3221_14 Datasheet, PDF (22/30 Pages) Texas Instruments – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3221, DS92LV3222
SNLS319C – OCTOBER 2009 – REVISED APRIL 2013
APPLICATIONS INFORMATION
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TRANSMISSION MEDIA
The SER and DES are used in AC-coupled point-to-point configurations, through a PCB trace, or through twisted
pair cables. Interconnect for LVDS typically has a differential impedance of 100 Ohms. Use cables and
connectors that have matched differential impedance to minimize impedance discontinuities. In most applications
that involve cables, the transmission distance will be determined on data rates involved, acceptable bit error rate
and transmission medium.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SER/DES devices should be designed to provide low-noise
power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs
to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommended at the point of
power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with vias on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing,
multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of
interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
PLUG AND GO
The Serializer and Deserializer devices support hot plugging of the serial interconnect. The automatic receiver
lock to random data “plug & go” capability allows the DS92LV3222 to obtain lock to the active data stream during
a live insertion event.
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