DS92LV3221_14 Datasheet, PDF (17/30 Pages) Texas Instruments – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

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TxCLKIN
DS92LV3221, DS92LV3222
SNLS319C – OCTOBER 2009 – REVISED APRIL 2013
PDB (High)
BISTEN
2.0V
0.8V
BIST disabled
BIST enabled
BIST disabled
4 x tCIP
4 x tCIP
Figure 16. BIST Test Enabled/Disabled
Under the BIST mode, the DES parallel outputs on RxOUT[31:0] are multiplexed to represent BIST status
indicators. The pass/fail status of the BIST is represented by a Pass flag along with an Error counter. The Pass
flag output is designated on DES RxOUT0 for Channel 0, and RxOUT16 for Channel 1. The DES's PLL must first
be locked to ensure the Pass status is valid. The output Pass status pin will stay LOW and then transition to High
once 44*10^6 symbols are achieved across each of the respective transmission links. The total time duration of
the test is defined by the following: 44*10^6 x tCIP . After the Pass output flags reach a HIGH state, it will not
drop to LOW even if subsequent bit errors occurred after the BIST duration period. Errors will be reported if the
input test pattern comparison does not match. If an error (miss-compare) occurs, the status bit is latched on
RxOUT[7:1] for Channel 0, and RxOUT[23:17] for Channel 1; reflecting the number of errors detected. Whenever
a data bit contains an error, the Error counter bit output for that corresponding channel goes HIGH. Each counter
for the serial link utilizes a 7-bit counter to store the number of errors detected (0 to 127 max).
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