DS92LV3221_14 Datasheet, PDF (20/30 Pages) Texas Instruments – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3221, DS92LV3222
SNLS319C – OCTOBER 2009 – REVISED APRIL 2013
3.3V
3.3V
1.8V or 3.3V
VDDA
VDDPLL
VDDPLL
IOVDD
TxCLKIN
TxIN31
TxIN30
TxIN29
TxIN28
TxIN27
TxIN26
TxIN25
TxIN24
TxIN23
TxIN22
TxIN21
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
PDB
BISTEN
Notes:
Caps are 0.1 PF
except Bulk Supply (4.7 PF)
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSSPLL
VSSPLL
VSSA
IOVSS
TxOUT0+
TxOUT0-
TxOUT1+
TxOUT1-
PRE
R_FB
VSEL
RSVD1
RSVD2
3.3V
opt.
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Figure 18. DS92LV3221 Typical Connection Diagram
Figure 19 shows a typical application of the DS92LV3222 Deserializer (DES). The differential inputs utilize 100nF
coupling capacitors in the serial lines. Bypass capacitors are placed near the power supply pins. A system GPO
(General Purpose Output) controls the PDB pin. In this application the R_FB (DES) pin is tied Low to strobe the
data on the falling edge of the RxCLKOUT. The REN signal is not used and is tied High also.
Configuration pins for the typical application are shown for DES:
• PDB – Power Down Control Input – Connect to host or tie HIGH
• REN – tie HIGH if not used (used to MUX two DES to one target device)
• RSVD – tie LOW
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