DS92LV3221_14 Datasheet, PDF (7/30 Pages) Texas Instruments – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3221, DS92LV3222
www.ti.com
SNLS319C – OCTOBER 2009 – REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾
Symbol
Parameter
Conditions
Min
V_OH
High Level Output Voltage
V_OL
Low Level Output Voltage
I_OS
Output Short Circuit Current
I_OZ
TRI-STATE Output Current
SERIALIZER LVDS DC SPECIFICATIONS
I_OH = −2mA
I_OH = −2mA
V_OUT = 0V
PDB = 0V,
V_OUT = 0V or V_DD
2.4
GND
−10
V_OD
Output Differential Voltage
No pre-emphasis, VSEL = L
(VSEL = H)
350
(629)
ΔV_OD
V_OS
ΔV_OS
I_OS
Output Differential Voltage Unbalance
Offset Voltage
Offset Voltage Unbalance
Output Short Circuit Current
VSEL = L, No pre-emphasis
VSEL = L, No pre-emphasis
VSEL = L, No pre-emphasis
TxOUT[1:0] = 0V, PDB = V_DD,
VSEL = L, No pre-emphasis
1.00
−2
TxOUT[1:0] = 0V, PDB = V_DD,
VSEL = H, No pre-emphasis
−6
I_OZ
TRI-STATE Output Current
PDB = 0V, TxOUT[1:0] = 0V OR V_DD
−15
PDB = V_DD, TxOUT[1:0] = 0V OR V_DD
−15
R_T
Output Termination
Internal differential output termination
between differential pairs
90
SERIALIZER SUPPLY CURRENT (DVDD, PVDD AND AVDD PINS)⁽³⁾
I_DDTD
Serializer (Tx) Total Supply Current
(includes load current)
f= 50 MHz, CHECKER BOARD pattern
VSEL = H, PRE = OFF
f= 50 MHz, CHECKER BOARD pattern
VSEL = H, RPRE = 12 kΩ
f= 50 MHz, RANDOM pattern
VSEL = H, PRE = OFF
f= 50 MHz, RANDOM pattern
VSEL = H, RPRE = 12 kΩ
I_DDTZ
Serializer Supply Current
Power-down
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
DESERIALIZER LVDS DC SPECIFICATIONS
V_TH
Differential Threshold High Voltage
V_CM = +1.8V
V_TL
Differential Threshold Low Voltage
−50
R_T
Input Termination
Internal differential output termination
between differential pairs
90
I_IN
Input Current
V_IN = +2.4V, V_DD = 3.6V
V_IN = 0V, V_DD = 3.6V
DESERIALIZER SUPPLY CURRENT (DVDD, PVDD AND AVDD PINS)⁽³⁾
f = 50 MHz, C_L = 8 pF,
CHECKER BOARD pattern
f = 50 MHz, C_L = 8 pF,
RANDOM pattern
I_DDRZ
Deserializer Supply Current Power-down PDB = 0V
(All other LVCMOS Inputs = 0V,
RxIN[1:0](P/N) = 0V)
(3) DIGITAL, PLL, AND ANALOG VDDS
Typ
Max Units
3.0
V_DD
V
0.33
0.5
V
−22
−40
mA
+10
μA
440
(850)
1
1.25
4
−5
−10
±1
±1
100
525
(1000)
50
1.50
50
mV_P-P
mV_P-P
V
mV
mA
+15
µA
+15
µA
130
Ω
120
145
120
145
mA
115
135
115
135
2
50
µA
+50
mV
mV
100
130
Ω
±100 ±250
µA
±100 ±250
µA
145
185
mA
122
140
100
µA
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