DS92LV3221_14 Datasheet, PDF (23/30 Pages) Texas Instruments – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3221, DS92LV3222
www.ti.com
SNLS319C – OCTOBER 2009 – REVISED APRIL 2013
LVDS INTERCONNECT GUIDELINES
For full details, see the Channel-Link PCB and Interconnect Design-In Guidelines (literature number SNLA008)
and the Transmission Line RAPIDESIGNER Operation and Applications Guide (literature number SNLA035).
• Use 100 Ohm coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual (literature number SNLA187), which is
available in PDF format from the TI LVDS & CML Solutions web site.
The waveforms below illustrate the typical performance of the DS92LV3221. The SER was given a PCLK and
configured as described below each picture. In all of the pictures the SER was configured with BISTEN pin set to
logic HIGH. Each waveform was taken by using a high impedance low capacitance differential probe to probe
across a 100 ohm differential termination resistor within one inch of TxOUT0+/-.
Figure 20. Serial Output, 50 MHz, VSEL = H,
No Pre-Emphasis
Figure 21. Serial Output, 50 MHz, VSEL = L,
No Pre-Emphasis
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