DS92LV3221_14 Datasheet, PDF (5/30 Pages) Texas Instruments – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3221, DS92LV3222
www.ti.com
SNLS319C – OCTOBER 2009 – REVISED APRIL 2013
DS92LV3222 DESERIALIZER PIN DESCRIPTIONS
Pin #
Pin Name
I/O, Type
Description
LVCMOS PARALLEL INTERFACE PINS
5–7,
10–14,
19–25,
28–32,
33–39,
42–46
RxOUT[31:29],
RxOUT[28:24],
RxOUT[23:17],
RxOUT[16:12],
RxOUT[11:5],
RxOUT[4:0]
O, LVCMOS Deserializer Parallel Interface Data Output Pins.
4
RxCLKOUT
O, LVCMOS Deserializer Recovered Clock Output. Parallel data rate clock recovered from the embedded
clock.
3
LOCK
O, LVCMOS LOCK indicates the status of the receiver PLL LOCK = L; deserializer CDR/PLL is not locked,
RxOUT[31:0] and RCLK are TRI-STATED
LOCK = H; deserializer CDR/PLL is locked
CONTROL AND CONFIGURATION PINS
48
R_FB
I, LVCMOS
Rising/Falling Bar Clock Edge Select
R_FB = H; RxOUT clocked on rising edge
R_FB = L; RxOUT clocked on falling edge
50
REN
I, LVCMOS
Deserializer Enable, DES Output Enable Control Input (ACTIVE HIGH)
REN = L; disabled, RxOUT[31:0] and RxCLKOUT TRI-STATED, PLL still operational
REN = H; Enabled (ACTIVE HIGH)
49
PDB
I, LVCMOS
Power Down Bar, Control Input Signal (ACTIVE LOW)
PDB = L; disabled, RxOUT[31:0], RCLK, and LOCK are TRI-STATED in stand-by mode, PLL
is shutdown
PDB = H; Enabled
47
RSVD
I, LVCMOS Reserved — MUST BE TIED LOW
57, 58, NC
59, 60
Do Not Connect, leave pins floating
LVDS SERIAL INTERFACE PINS
51, 53 RxIN[0:1]+
I, LVDS
Deserializer LVDS Non-Inverted Inputs(+)
52, 54 RxIN[0:1]-
I, LVDS
Deserializer LVDS Inverted Inputs(-)
POWER / GROUND PINS
9, 16, VDD
17, 26,
61
VDD
Digital Voltage supply, 3.3V
8, 15, VSS
18, 27,
62
GND
Digital Ground
55
VDDA
VDD
Analog LVDS Voltage supply, POWER, 3.3V
56
VSSA
GND
Analog LVDS GROUND
1, 40, VDDPLL
64
VDD
Analog Voltage supply PLL VCO POWER, 3.3V
2, 41, VSSPLL
63
GND
Analog ground, PLL VCO GROUND
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DS92LV3221 DS92LV3222