DS92LV3221_14 Datasheet, PDF (12/30 Pages) Texas Instruments – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3221, DS92LV3222
SNLS319C – OCTOBER 2009 – REVISED APRIL 2013
PDB
2.0V
RxIN [1:0]+/-
LOCK
TRI-STATE
RxOUT [31:0] TRI-STATE
RxCLKOUT
TRI-STATE
t_RPLLS
0.8V
'RQ¶W &DUH
TRI-STATE
t_HZR or t_LZR
TRI-STATE
TRI-STATE
REN
Figure 11. Deserializer PLL Lock Time and PDB TRI-STATE Delay
REN
500:
V_REF
C_L = 8 pF
+
-
V_REF = V_DD/2 for t_ZLR or t_LZR
V_REF = 0V for t_ZHR or t_HZR
VOH
REN
VOL
V_DD/2
t_LZR
V_DD/2
t_ZLR
VOL
RxOUT [31:0]
VOH
t_HZR
VOL + 0.5V
t_ZHR
VOL + 0.5V
VOH - 0.5V
VOH + 0.5V
Note: C_L includes instrumentation and fixture capacitance within 6 cm of RxOUT [31:0].
Figure 12. Deserializer TRI_STATE Test Circuit and Timing
0
TxCLKIN = 50 MHz
-3
-6
-9
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
FREQUENCY (Hz)
Figure 13. Serializer Jitter Transfer
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