DS92LV3221_14 Datasheet, PDF (1/30 Pages) Texas Instruments – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3221, DS92LV3222
www.ti.com
SNLS319C – OCTOBER 2009 – REVISED APRIL 2013
DS92LV3221/DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer
Check for Samples: DS92LV3221, DS92LV3222
FEATURES
1
•2 Wide Operating Range Embedded Clock
SER/DES
– Up to 32-bit Parallel LVCMOS Data
– 20 to 50 MHz Parallel Clock
– Up to 1.6 Gbps Application Data Paylod
• Simplified Clocking Architecture
– No Separate Serial Clock Line
– No Reference Clock Required
– Receiver Locks to Random Data
• On-chip Signal Conditioning for Robust Serial
Connectivity
– Transmit Pre-Emphasis
– Data Randomization
– DC-Balance Encoding
– Receive Channel Deskew
– Supports up to 10m CAT-5 at 1.6Gbps
• Integrated LVDS Terminations
• Built-in AT-SPEED BIST for End-To-End
System Testing
• AC-Coupled Interconnect for Isolation and
Fault Protection
• > 4KV HBM ESD Protection
• Space-Saving 64-pin TQFP Package
• Full Industrial Temperature Range: -40° to
+85°C
APPLICATIONS
• Industrial Imaging (Machine-vision) and
Control
• Security and Surveillance Cameras and
Infrastructure
• Medical Imaging
DESCRIPTION
The DS92LV3221 (SER) serializes a 32-bit data bus
into 2 embedded clock LVDS serial channels for a
data payload rate up to 1.6 Gbps over cables such as
CATx, or backplanes FR-4 traces. The companion
DS92LV3222 (DES) deserializes the 2 LVDS serial
data channels, de-skews channel-to-channel delay
variations and converts the LVDS data stream back
into a 32-bit LVCMOS parallel data bus.
On-chip data Randomization/Scrambling and DC
balance encoding and selectable serializer Pre-
emphasis ensure a robust, low-EMI transmission over
longer, lossy cables and backplanes. The
Deserializer automatically locks to incoming data
without an external reference clock or special sync
patterns, providing an easy “plug-and-lock” operation.
By embedding the clock in the data payload and
including signal conditioning functions, the Channel-
Link II SerDes devices reduce trace count, eliminate
skew issues, simplify design effort and lower
cable/connector cost for a wide variety of video,
control and imaging applications. A built-in AT-
SPEED BIST feature validates link integrity and may
be used for system diagnostics.
BLOCK DIAGRAM
TxCLKIN
PLL
TxIN0
High-Speed
Serial Data
100: differential pairs
CDR/PLL
RxCLKOUT
RxOUT0
TxIN15
TxIN16
TxIN31
PDB
R_FB
BISTEN
MODE
VSEL
PRE
BIST
Control
TxOUT0+
TxOUT0 -
TxOUT1+
TxOUT1 -
Pre-Emp
RxIN0+
RxIN0 -
RxIN1 +
RxIN1 -
REN
R_FB
PDB
RxOUT15
RxOUT16
RxOUT31
BIST
Control
LOCK
Tx - SERIALIZER
Rx - DESERIALIZER
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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