DS90UR910-Q1 Datasheet, PDF (8/34 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

DS90UR910-Q1
SNLS414D – JUNE 2012 – REVISED JULY 2015
5.5 AC Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
FPD-LINK II RECEIVER (RIN±)
t_IJT
Input Jitter Tolerance, Figure 1
EQ = OFF,
jitter freq < 2MHz
0.9
PCLK = 65MHz _{jitter freq > 6MHz}
0.5
t_DDLT
Deserializer Lock Time, Figure 2
PCLK = 75 MHz
10
HSTX DRIVER AC SPECIFICATIONS (DATA0±, DATA1±, CLK±) Section 8.1.1 of MIPI D-PHY Specification
HSTX_DBR
Data bit rate
DATA0±
DATA1±
PCLK = 10-75MHz
(2)
120
PCLK*12
f_CLK
ΔV_CMTX(HF)
DDR Clock frequency
Common mode voltage variations
HF
CLK±
Common-level variations above 450
MHz ⁽²⁾
60
PCLK*6
ΔV_CMTX(LF)
Common mode voltage variations LF Common-level variations between
50–450 MHz ⁽²⁾
t_RHS
Rise Time HS
20% to 80% rise time ⁽³⁾
150
t_FHS
Fall Time HS
20% to 80% rise time ⁽³⁾
150
SDD_TX
TX differential return loss
See Figure 33 of
MIPI D-PHY
Specification ⁽²⁾
f_LPMAX
f_H
f_MAX
SCC_TX
TX common mode return loss
Section 7.7.2 of f_LPMAX to f_MAX
MIPI D-PHY
Specification ⁽²⁾
LPTX DRIVER AC SPECIFICATIONS (DATA0±, DATA1±, CLK±) ⁽⁴⁾
Section 8.1.2 of MIPI D-PHY Specification
t_RLP
Rise Time
LP 15% to 85% rise time
Cload = 70pF lumped capacitance
t_FLP
Fall Time
LP 15% to 85% fall time
Cload = 70pF lumped capacitance
t_REOT
Post-EoT Rise and Fall Time
30%-85% rise time and fall time ⁽²⁾
t_LP-PULSE-TX Pulse width of the LP exclusive-OR First LP exclusive-OR clock pulse
clock
after Stop state or last pulse before
40
Stop state ⁽²⁾
All other pulses ⁽²⁾
20
t_LP-PER-TX
Period of the LP exclusive-OR clock See ⁽²⁾
90
www.ti.com
Max
Units
UI ⁽¹⁾
UI
ms
900
Mbps
450
MHz
15
mV_RMS
25
mV_PEAK
0.3
UI_INST
ps
0.3
UI_INST
ps
–18
dB
–12
dB
–6
dB
–6
dB
25
ns
25
ns
35
ns
ns
ns
ns
(1) UI is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency.
(2) Specification is ensured by design and is not tested in production.
(3) Specification is ensured by characterization.
(4) CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be
<10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2ns delay.
8
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS90UR910-Q1