DS90UR910-Q1 Datasheet, PDF (18/34 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

DS90UR910-Q1
SNLS414D – JUNE 2012 – REVISED JULY 2015
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6.3 Feature Description
6.3.1 Input Receive Equalization
The input equalizer of the DS90UR910-Q1 is designed to compensate the attenuation distortion results from
cable of different length or wire gauge. The equalizer gain setting is controlled by the control pins EQ[3:1] or
through register programming. Users can optimize the equalizer’s gain setting along with the de-emphasis level
of the DS90UR905Q/907Q to achieve the optimum jitter performance.
Note this function cannot be seen at the RIN+/- input but can be observed at the serial test port (CMLOUT+/-)
enabled via the Serial Bus control registers. The equalization feature may be controlled by the external pin or by
register.
EQ3
0
0
0
1
1
1
1
0
(1) Default Setting is EQ = Off
Table 2. Receiver Equalization Configuration
INPUTS EQ[3:1]
EQ2
0
1
1
0
0
1
1
0
EQ1
1
0
1
0
1
0
1
0
EQ Boost
~3 dB
~4.5 dB
~6 dB
~7.5 dB
~9 dB
~10.5 dB
~12 dB
See ⁽¹⁾
6.3.2 CSI-2 Interface
The DS90UR910-Q1 (in default mode) takes the RGB data bits R[7:0], G[7:0] and B[7:0] defined in the 24-bit
serializer pinout and directly maps to the RGB888 color space in the data frame. The DS90UR910-Q1 follows the
General Frame Format as described in Figure 49 of the CSI-2 standard (repeated here in Figure 11). Upon the
end of the vertical sync pulse (VS), the DS90UR910-Q1 generates the Frame End and Frame Start
synchronization packets within the vertical blanking period. The timing of the Frame Start will not reflect the
timing of the VS signal.
Upon the rising edge of the DE signal, each active line is output in a long data packet with the RGB888 data
format. At the end of each packet, the data lanes DATA0± and DATA1± return to the LP-11 state, while the clock
lane CLK± continue outputting the high speed clock.
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