DS90UR910-Q1 Datasheet, PDF (28/34 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

DS90UR910-Q1
SNLS414D – JUNE 2012 – REVISED JULY 2015
7 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Typical Application Connection
Figure 16 shows a typical application of the DS90UR910-Q1 in Pin control mode for a 24-bit Color Display
Application. The LVDS signals require 100 nF AC coupling capacitors to the line. The line driver includes internal
termination. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1 µF capacitors and
a 4.7 µF capacitor should be used for local device bypassing. System GPO (General Purpose Output) signals
control the PDB and BISTEN pins. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO pin is
connected also to the 1.8V rail. The Optional I2C/CCI is connected to the Host bus in this example, thus the SCL
and SDA pins are using pull-up resistors R to VDDIO. A delay cap is placed on the PDB signal to delay the
enabling of the device until power is stable.
1.8V
FB1
1.8V
3.3V
FB1, FB2:
1 NŸ @100 MHz
DC R < 1Ÿ
2.2 µF
ceramic
FB2
0.1 µF
0.1 µF
VDDCSI VDDL
0.1 µF
4.7 µF
ceramic
2.2 µF
0.1 µF _ceramic
VDDA
0.1 µF VDDP
VDDIO
0.1 µF
Data1+
Data1-
From FPD-Link II
Serializer
100Ÿ 673
4.7 µF
ceramic
0.1 µF
RIN+
CMF
RIN-
Data0+
Data0-
CLK+
CLK-
DS90UR910-Q1
VDDIO
RR
GPU
100: (1%)
Strap
High or Low
CMLOUT+
SCL
SDA
CMLOUT-
CONFIG[1:0]
EQ[3:1]
ID[1:0]
RES
GND
DAP
LOCK
BISTEN
PASS
PDB
Optional
Control pins
VDDIO
10 k:
10 µF
Figure 16. DS90UR910-Q1 Typical Connection Diagram — Pin Control
7.2 Design Requirements
For the typical design application, use the following as input parameters.
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