DS90UR910-Q1 Datasheet, PDF (23/34 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

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DS90UR910-Q1
SNLS414D – JUNE 2012 – REVISED JULY 2015
Single Read from random location
SLAVE
SUB
S _ADDRESS 0 A _ADDRESS
A
S
r
SLAVE
ADDRESS
1A
DATA
AP
Single Read from the current location
SLAVE
S _ADDRESS 1 A DATA A P
Sequential Read from a random location
SLAVE
SUB
S _ADDRESS 0 A _ADDRESS
A
S
r
SLAVE
ADDRESS
1A
DATA
A
DATA A P
Sequential Read from current location
SLAVE
S _ADDRESS 1 A
DATA
A
DATA
A
Single Write from random location
SLAVE
SUB
S _ADDRESS 0 A _ADDRESS A
DATA
A/
A
P
DATA A P
Sequential Write
SLAVE
SUB
S _ADDRESS 0 A _ADDRESS A
DATA
A
DATA
A/
A
P
Figure 14. I2C/CCI Read/Write Operations
6.3.7 Ultra Low Power State
DS90UR910-Q1 D-PHY Lanes will enter ULPS mode upon software standby mode through CCI generated by
Application Processor. When ULPS is entered, all lanes including the clock and data lanes are put in ULPS
according to the MIPI D-PHY protocol. D-PHY can reduce power consumption by entering ULPS mode.
Ultra-Low Power State Entry Command is sent after an Escape mode Entry command through CCI, and then
Lane shall enter the Ultra-Low Power State (ULPS). When ULPS is entered, all lanes including the clock and
data lanes are put in ULPS according to the MIPI DPHY protocol. Typically an ULPS entry command is used but
other sequences can be used also. Ultra-Low Power State is exited by means of a Mark-1 state with a length
TWAKEUP followed by a Stop state. Reference: [1] D-PHY Specification, Section 5.6.3, Line 895
Frame
End
Stop Escape
(LP11) Mode
Ultra-Low-Power-State Entry Command 00011110
Clock Lane
Dp/Dn
ULPS
(LP00)
Mark-1
(LP10)
Stop
(LP11)
Data Lane
Dp/Dn
tLPX
tWAKEUP tINIT
Figure 15. Ultra-Low Power State
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