DS90UR910-Q1 Datasheet, PDF (22/34 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

DS90UR910-Q1
SNLS414D – JUNE 2012 – REVISED JULY 2015
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The Serial Bus protocol is initiated by START or START-REPEATED, and terminated by STOP condition. A
START occurs when SDA transitions low while SCL is high. A STOP occurs when SDA transitions high when
SCL is high. See Figure 13.
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 13. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the 7-bit slave address followed by a
write-bit (0), and listens for a response from the slave. This response is referred to as an acknowledge bit. If the
slave on the bus is addressed correctly, it acknowledges the master by driving the SDA low (ACK). If the address
does not match a device’s slave address, it negative acknowledges the master by letting SDA be pulled high
(NACK). In a write operation from master to slave, the master sends the 8-bit index address of the register that it
wants to access. After the slave ACKs, the master sends the 8-bit data byte. The slave ACKs after each data
byte is successfully received and is ready to receive another byte into the next sequential index location. At the
end of the data transfer, the master ends the transaction with a STOP condition.
In a read operation, the master first sends the 8-bit index address of the register that it wants to access. After
receiving an ACK from the slave, it initiates a START-REPEAT condition, sends the 7-bit slave address followed
by the read-bit (1). The slave ACKs and sends out the 8-bit data byte. The master acknowledges an ACK when
another data byte will be sent to the next sequential index address. The master acknowledges an NACK when
no more data byte will be sent, and ends the transaction with a STOP condition.
The CCI interface of the DS90UR910-Q1 supports Standard mode (<100KHz) or Fast mode (<400KHz) with 8-bit
index addressing and 8-bit data transfer. It supports the following read/write operations between the
DS90UR910-Q1 and the CCI master:
• Single read from random location
• Single read from current location
• Sequential read starting from a random location
• Sequential read starting from the current location
• Single write to a random location
• Sequential write starting from a random location
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