DS90UR910-Q1 Datasheet, PDF (26/34 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

DS90UR910-Q1
SNLS414D – JUNE 2012 – REVISED JULY 2015
Register Maps (continued)
ADD
(hex)
0x11
Register Name
CSI config
Table 7. Serial Bus Control Registers (continued)
Bit(s) R/W Default Field
7
R/W
0
CCI_INV_VS
6
R/W
0
CCI_CONT_CLOCK
5:2 R/W
1
R/W
0
Reserved
0
CCI_EXTERNAL_TIMING
0x12 CSI_FRM_GAP_0
0x13 CSI_FRM_GAP_1
0x14 CSI_TIMING0
0
R/W
7:0 R/W
7:0 R/W
7:5
4:0 R/W
0
CCI_INV_DE
0
CSI_FRM_GAP_0
0
CSI_FRM_GAP_1
0
Reserved
0
TCLK_PREPARE
0x15 CSI_TIMING1
7:3 R/W
0
TCLK_ZERO
2:0 R/W
0
TCLK_TRAIL
0x16 CSI_TIMING2
7:4 R/W
0
TCLK_POST
3:0 R/W
0
THS_ZERO
0x17 CSI_TIMING3
7
R/W
6:4 R/W
0
Reserved
0
THS_TRAIL
3:0 R/W
0
THS_EXIT
0x18 CSI_TIMING4
7:3 R/W
0
THS_PREPARE
2:0 R/W
0
TLPX
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Description
0: VS is active low pulse
1: VS is active high pulse
0: CSI-2 non-continuous clock
1: CSI-2 continuous clock
Reserved
0: Use computed DPHY timing
based on frame length
1: Use manual override values
for DPHY timing
0: DE is active low pulse
1: DE is active high pulse
Defined the delay between the
start frame and end frame
packet (lower byte)
Defined the delay between the
start frame and end frame
packet (upper byte)
Reserved
Defines the Tclk_prepare
parameter if
CCI_EXTERNAL_TIMING is
set
Defines the Tclk_zero
parameter if
CCI_EXTERNAL_TIMING is
set
Defines the Tclk_trail
parameter if
CCI_EXTERNAL_TIMING is
set
Defines the Tclk_post
parameter if
CCI_EXTERNAL_TIMING is
set
Defines the Ths_zero
parameter if
CCI_EXTERNAL_TIMING is
set
Reserved
Defines the Ths_trail
parameter if
CCI_EXTERNAL_TIMING is
set
Defines the Ths_exit
parameter if
CCI_EXTERNAL_TIMING is
set
Defines the Ths_prepare
parameter if
CCI_EXTERNAL_TIMING is
set
Defines the Ths_exit
parameter if
CCI_EXTERNAL_TIMING is
set
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