DS90UR907Q-Q1 Datasheet, PDF (8/35 Pages) Texas Instruments – 24-Bit Color FPD-Link to FPD-Link II Converter

DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
Recommended Timing for the Serial Control Bus (continued)
Over 3.3-V supply and temperature ranges unless otherwise specified.
t_SU;STO
t_BUF
t_r
t_f
Set Up Time for STOP
Condition, Figure 12
Bus Free Time
Between STOP and START,
Figure 12
SCL and SDA Rise Time,
Figure 12
SCL and SDA Fall Time,
Figure 12
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast mode
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MIN NOM MAX Units
4
us
0.6
4.7
us
1.3
1000
ns
300
300
ns
300
6.8 Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
FPD-LINK LVDS INPUT
t_RSP0 Receiver Strobe Position-bit 0
t_RSP1 Receiver Strobe Position-bit 1
t_RSP2 Receiver Strobe Position-bit 2
t_RSP3 Receiver Strobe Position-bit 3
t_RSP4 Receiver Strobe Position-bit 4
t_RSP5 Receiver Strobe Position-bit 5
t_RSP6 Receiver Strobe Position-bit 6
FPD-LINK II LVDS OUTPUT
RxCLKIN = 65 MHz,
RxIN[3:0]
Figure 5
t_HLT
Output Low-to-High Transition R_L = 100 Ω, De-Emphasis = disabled, VODSEL = 0
Time, Figure 4
R_L = 100 Ω, De-Emphasis = disabled, VODSEL = 1
t_HLT
Output High-to-Low Transition R_L = 100 Ω, De-Emphasis = disabled, VODSEL = 0
Time, Figure 4
R_L = 100 Ω, De-Emphasis = disabled, VODSEL = 1
t_XZD
Ouput Active to OFF Delay,
Figure 7
t_PLD
PLL Lock Time, Figure 6
R_L = 100 Ω⁽¹⁾
t_SD
Delay - Latency, Figure 8
R_L = 100 Ω
t_DJIT
Output Total Jitter,
Figure 9
R_L = 100 Ω, De-Emphasis = disabled,
RANDOM pattern, RxCLKIN = 43 and 65 MHz⁽²⁾
λ_STXBW Jitter Transfer
RxCLKIN = 43 MHz
Function –3-dB Bandwidth^{(3) (4)} _{RxCLKIN = 65 MHz}
δ_STX
Jitter Transfer
Function Peaking⁽³⁾⁽⁴⁾
RxCLKIN = 43 MHz
RxCLKIN = 65 MHz
MIN TYP MAX UNIT
0.66
2.86
5.05
7.25
9.45
11.65
13.85
1.1
3.3
5.5
7.7
9.90
12.1
14.30
1.54 ns
3.74 ns
5.93 ns
8.13 ns
10.33 ns
12.53 ns
14.73 ns
200
200
200
200
5
1.5
140*T
0.26
2.2
3
1
1
ps
ps
15 ns
10 ms
145*T ns
UI
MHz
dB
(1) t_PLD is the time required by the device to obtain lock when exiting power-down state with an active RxCLKIN.
(2) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*RxCLKIN). The UI scales with RxCLKIN frequency.
(3) Specification is ensured by characterization and is not tested in production.
(4) Specification is ensured by design and is not tested in production.
6.9 DC and AC Serial Control Bus Characteristics
Over 3.3-V supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
V_IH
Input High Level
SDA and SCL
V_IL
Input Low Level Voltage
SDA and SCL
V_HY
Input Hysteresis
MIN
0.7*
V_DDIO
GND
TYP
>50
MAX UNIT
V_DDIO V
0.3*
V_DDIO
V
mV
8
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