DS90UR907Q-Q1 Datasheet, PDF (4/35 Pages) Texas Instruments – 24-Bit Color FPD-Link to FPD-Link II Converter

DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
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Pin Functions (continued)
NAME
PIN
NO.
I/O, TYPE
DESCRIPTION
CONTROL AND CONFIGURATION
PDB
Power-down Mode Input
PDB = 1, Device is enabled (normal operation).
23
I, LVCMOS Refer to Power-Up Requirements and PDB Pin in the Applications Information Section.
w/ pulldown PDB = 0, Device is powered down
When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic
high, the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL
Differential Driver Output Voltage Select — Pin or Register Control
20
I, LVCMOS VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typical) — Long Cable / De-E
w/ pulldown Applications
VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typical)
De-Emph
De-Emphasis Control — Pin or Register Control
19
I, Analog De-Emph = open (float) - disabled
w/ pullup To enable De-emphasis, tie a resistor from this pin to GND or control through register.
See Table 3
MAPSEL
26
I, LVCMOS
w/ pulldown
FPD-Link Map Select — Pin or Register Control
MAPSEL = 1, MSB on RxIN3+/-. Figure 17
MAPSEL = 0, LSB on RxIN3+/-. Figure 16
CONFIG[1:0]
10, 9
I, LVCMOS
w/ pulldown
Operating Modes
Determine the device operating mode and interfacing device. Table 1
CONFIG[1:0] = 00: Interfacing to DS90UR906 or DS90UR908, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR906 or DS90UR908, Control Signal Filter
ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124
CONFIG [1:0] = 11: Interfacing to DS90C124
ID[x]
4
I, Analog
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10-kΩ pullup to 1.8-V rail. See Table 5.
SCL
SDA
BISTEN
6
I, LVCMOS
Serial Control Bus Clock Input - Optional
SCL requires an external pullup resistor to V_DDIO.
7
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pullup resistor V_DDIO.
21
I, LVCMOS
w/ pulldown
BIST Mode — Optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES[7:0]
25, 3, 36, 27,
18, 13, 12, 8
I, LVCMOS
w/ pulldown
Reserved - tie LOW
FPD-LINK II SERIAL INTERFACE
DOUT+
16
O, LVDS
True Output.
The output must be AC Coupled with a 100 nF capacitor.
DOUT-
15
O, LVDS
Inverting Output.
The output must be AC Coupled with a 100 nF capacitor.
POWER AND GROUND
VDDL
5
Power Logic Power, 1.8 V ±5%
VDDP
11
Power PLL Power, 1.8 V ±5%
VDDHS
14
Power TX High Speed Logic Power, 1.8 V ±5%
VDDTX
17
Power Output Driver Power, 1.8 V ±5%
VDDRX
24
Power RX Power, 1.8 V ±5%
V_DDIO
GND
22
DAP
Power
Ground
LVCMOS I/O Power and FPD-Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
4
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