DS90UR907Q-Q1 Datasheet, PDF (26/35 Pages) Texas Instruments – 24-Bit Color FPD-Link to FPD-Link II Converter

DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
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Refer to the Table 3. The PDB and BISTEN pins are assumed controlling by a microprocessor. The PDB must
be low state until all power supply voltages reach the final voltage. The CONFIG[1:0] pins are set depending on
operating modes and interfacing device. See the Table 1. MAPSEL pin is set the mapping scheme. Refer to the
Figure 16 and Figure 17. The SCL, SDA, and ID[x] pins are left open when these Serial Bus Control pins are
unused. The RES[7:0] pins and DAP should be tied to ground.
8.2.3 Application Curves
Serializer CML Output Stream with Input PCLK = 65 MHz, VODSEL = L Serializer CML Output Stream with Input PCLK = 65 MHz, VODSEL = H
Figure 26. Serializer CML Output Stream With Input PCLK
= 65 MHz, VODSEL = L
Figure 27. Serializer CML Output Stream With Input
PÄCLK = 65 MHz, VODSEL = H
9 Power Supply Recommendations
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower than 1.5
ms, then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to VDDIO, TI recommends using a 10-kΩ pullup and a
>10-μF capacitor to GND to delay the PDB input signal.
All inputs must not be driven until all supply voltages have reached their steady-state value.
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