DS90UR907Q-Q1 Datasheet, PDF (17/35 Pages) Texas Instruments – 24-Bit Color FPD-Link to FPD-Link II Converter

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RESISTOR VALUE (kΩ)
Open
0.6
1
2
5
DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
Table 3. De-Emphasis Resistor Value
DE-EMPHASIS SETTING
Disabled
–12 dB
–9 dB
–6 dB
–3 dB
0.00
-2.00
VDD = 1.8V,
T_A = 25^oC
-4.00
-6.00
-8.00
-10.00
-12.00
-14.00
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
R VALUE - LOG SCALE (:)
Figure 18. De-Emph vs R Value
7.3.7 Power Saving Features
7.3.7.1 Power-Down Feature (PDB)
The DS90UR907Q has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the
host and is used to save power, disabling the link when the display is not needed. In the POWER DOWN mode,
the high-speed driver outputs present a 0V VOD state. Note – in POWER DOWN, the optional Serial Bus Control
Registers are RESET.
7.3.7.2 Stop Clock Feature
The DS90UR907Q enters a low power SLEEP state when the RxCLKIN is stopped. A STOP condition is
detected when the input clock frequency is less than 3 MHz. The clock should be held at a static Low or high
state. When the RxCLKIN starts again, the device will then lock to the valid input RxCLKIN and then transmits
the RGB data to the deserializer. Note – in STOP CLOCK SLEEP, the optional Serial Bus Control Registers
values are RETAINED.
7.3.7.3 1.8-V or 3.3-V V_DDIO Operation
The DS90UR907Q parallel control bus operate with 1.8-V or 3.3-V levels (V_DDIO) for host compatibility. The 1.8-V
levels will offer a system power savings.
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