DS90UR907Q-Q1 Datasheet, PDF (25/35 Pages) Texas Instruments – 24-Bit Color FPD-Link to FPD-Link II Converter

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Typical Application (continued)
DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
VDDIO
C10 C8
FPD-Link
Interface
Host
Control
FB1
C3
DS90UR907Q
VDDIO
VDDTX
VDDHS
C4
FB2
1.8V
C9 C11
100:
100:
100:
100:
100:
1.8V
10k
RID
RxCLKIN-
RxCLKIN+
RxIN3-
RxIN3+
RxIN2-
RxIN2+
RxIN1-
RxIN1+
RxIN0-
RxIN0+
ID[X]
SCL
SDA
VDDP
C12 C5
VDDL
C6
VDDRX
C7
DOUT+
DOUT-
FB3
FB4
FB5
C1
C2
VODSEL
De-Emph
VDDIO
R1
Serial
FPD-Link II
Interface
BISTEN
PDB
R
C13
CONFIG1
CONFIG0
MAPSEL
RES7
RES6
RES5
RES4
RES3
RES2
RES1
RES0
DAP (GND)
NOTE:
C1-C2 = 0.1 PF (50 WV)
C3-C9 = 0.1 PF
C10-C12 = 4.7 PF
C13 = >10 PF
R = 10 k:
R1 (cable insertion loss specific)
RID (see ID[x] Resistor Value Table)
FB1-FB5: Impedance = 1 k:,
low DC resistance (<1:)
Figure 25. Typical Connection Diagram
8.2.1 Design Requirements
Table 8 shows the input parameters for the typical design application.
Table 8. Design Parameters
DESIGN PARAMETER
VDDIO
VDDL, VDDP, VDDHS, VDDTX,
VDDRX
AC Coupling Capacitor for DOUT±
EXAMPLE VALUE
1.8 V or 3.3 V
1.8 V
100 nF
8.2.2 Detailed Design Procedure
The DOUT± outputs require 100-nF AC coupling capacitors to the line. FPD-Link data input pair required an
external 100-Ω termination for standard LVDS levels. The power supply filter capacitors are placed near the
power supply pins. A smaller capacitance capacitor should be located closer to the power supply pins. Adding a
ferrite bead is optional. Recommend to use 1-kΩ impedance and low DC resistance such as less than 1 Ω. The
VODSEL pin is tied to VDDIO for the long cable application. The De-Emph pin may connect a resistor to ground.
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