DS90UR907Q-Q1 Datasheet, PDF (24/35 Pages) Texas Instruments – 24-Bit Color FPD-Link to FPD-Link II Converter

DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
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Application Information (continued)
Table 7. Alternate Color / Data Mapping (continued)
FPD-Link
RxIN2
RxIN1
RxIN0
Bit Number
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RGB (LSB
Example)
DE
VS
HS
B7
B6
B5
B4
B3
B2
G7
G6
G5
G4
G3
G2
R7
R6
R5
R4
R3
R2
N/A
* These bits are not supported by DS90UR907Q
DS90UR907Q
Settings
MAPSEL = 0
DS90UR906Q DS90UR124 DS99R124Q
DE
VS
HS
B7
B6
B5
B4
B3
B2
G7
G6
G5
G4
G3
G2
R7
R6
R5
R4
R3
R2
N/A
CONFIG [1:0]
= 00
ROUT20
TxOUT2
ROUT19
ROUT18
ROUT17
ROUT16
ROUT15
ROUT14
ROUT13
TxOUT1
ROUT12
ROUT11
ROUT10
ROUT9
ROUT8
ROUT7
ROUT6
TxOUT0
ROUT5
ROUT4
ROUT3
ROUT2
ROUT1
ROUT0
ROUT23*
OS2*
ROUT22*
OS1*
ROUT21*
OS0*
CONFIG [1:0] = 10
DS90C124
ROUT20
ROUT19
ROUT18
ROUT17
ROUT16
ROUT15
ROUT14
ROUT13
ROUT12
ROUT11
ROUT10
ROUT9
ROUT8
ROUT7
ROUT6
ROUT5
ROUT4
ROUT3
ROUT2
ROUT1
ROUT0
ROUT23*
ROUT22*
ROUT21*
CONFIG [1:0]
= 11
8.2 Typical Application
Figure 25 shows a typical application of the DS90UR907Q for a 65-MHz 24-bit Color Display Application. The
LVDS inputs of the FPD-Link interface require external 100-Ω terminations. The LVDS outputs of FPD-Link II
require 100-nF AC coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors
are placed near the power supply pins. At a minimum, four 0.1-µF capacitors and a 4.7-µF capacitor should be
used for local device bypassing. System GPO (General Purpose Output) signals control the PDB and BISTEN
pins. The application assumes the companion deserializer (DS90UR908Q); therefore, the configuration pins are
also both tied Low. In this example the cable is long; therefore, the VODSEL pin is tied High and a De-Emphasis
value is selected by the resistor R1. The interface to the host is with 1.8-V LVCMOS levels, thus the VDDIO pin
is connected also to the 1.8-V rail. The Optional Serial Bus Control is not used in this example, thus the SCL,
SDA and ID[x] pins are left open. A delay capacitor and resistor is placed on the PDB signal to delay the
enabling of the device until power is stable. Bypass capacitors are placed near the power supply pins. Ferrite
beads are placed on the power lines for effective noise suppression.
24
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