DS90UR907Q-Q1 Datasheet, PDF (13/35 Pages) Texas Instruments – 24-Bit Color FPD-Link to FPD-Link II Converter

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7 Detailed Description
DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
7.1 Overview
The DS90UR907Q converter transmits an FPD-Link interface (4 LVDS data channels + 1 LVDS clock) with total
of 27–bits of data (24–high speed bits and 3 low speed video control signals) over a single serial FPD-Link II
pair. The serial stream also contains an embedded clock and the DC-balance information which enhances signal
quality and supports AC coupling. The device is intended for use with DS90UR908Q or DS90UR906Q, but is
backward compatible with previous generations of FPD-Link II as well.
The DS90UR907Q can operate in 24-bit color mode (with VS,HS,DE encoded in the serial stream) or in 18-bit
color mode.
The DS90UR907Q can be configured through external pins or through the optional serial control bus. It features
enhanced signal quality on the link by supporting: selectable VOD level, selectable deemphasis signal
conditioning and also the FPD-Link II data coding that provides randomization, scrambling, and DC Balancing of
the video data. It also includes multiple features to reduce EMI associated with display data transmission. This
includes the randomization and scrambling of the data and also the system spread spectrum PCLK support. The
DS90UR907Q features power saving with a power-down mode, and auto stop clock feature.
See also Built In Self Test (BIST) and Optional Serial Bus Control for more information.
7.2 Functional Block Diagram
VODSEL
De-Emph
RxIN3+/-
RxIN2+/-
RxIN1+/-
RxIN0+/-
RxCLKIN+/-
DOUT+
DOUT-
CONFIG[1:0]
MAPSEL
PDB
SCL
SDA
ID[x]
BISTEN
PLL
Pattern
Generator
Timing and
Control
FPD-Link to FPD-Link II Convertor
7.3 Feature Description
7.3.1 Data Transfer
The DS90UR907Q transmits a pixel of data in the following format: C1 and C0 represent the embedded clock in
the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain the scrambled RGB data. DCB is
the DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This
bit determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data
stream and can also contain encoded control (VS,HS,DE). Both DCA and DCB coding schemes are generated
by the DS90UR907Q and decoded by the paring deserializer automatically reference to FPD-Link II Serial
Stream. Figure 14 illustrates the serial stream per PCLK cycle.
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