DS90UR907Q-Q1 Datasheet, PDF (14/35 Pages) Texas Instruments – 24-Bit Color FPD-Link to FPD-Link II Converter

DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
Feature Description (continued)
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NOTE
The figure only illustrates the bits but does not actually represent the bit location as the
bits are scrambled and balanced continuously.
C
1
b
0
b
1
b
2
b
3
b
4
b
5
b
6
b
7
b
8
b
9
b
1
0
b
1
1
D
C
A
D
C
B
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
C
0
Figure 14. FPD-Link II Serial Stream
7.3.2 Operating Modes And Backward Compatibility - Config[1:0]
The DS90UR907Q is backward compatible with previous generations of FPD-Link II deserializers. Configuration
modes are provided for backwards compatibility with the DS90C124 FPD-Link II Generation 1, and also the
DS90UR124 FPD-Link II Generation 2 deserializers by setting the respective mode with the CONFIG[1:0] pins as
shown in Table 1. The selection also determine whether the Video Control Signal filter feature is enabled or
disabled in Normal mode.
CON
FIG1
L
L
H
H
CON
FIG0
L
H
L
H
Table 1. DS90UR907Q Configuration Modes
MODE
DES DEVICE
Normal Mode, Control Signal Filter disabled
Normal Mode, Control Signal Filter enabled
Backwards Compatible GEN2
Backwards Compatible GEN1
DS90UR908Q, DS90UR906Q
DS90UR908Q, DS90UR906Q
DS90UR124, DS99R124
DS90C124
7.3.3 Video Control Signal Filter
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3
PCLK or longer.
• Normal Mode with Control Signal Filter Disabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low-frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high-frequency
noise on the control signals. See Figure 15.
14
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