DS90UR907Q-Q1 Datasheet, PDF (23/35 Pages) Texas Instruments – 24-Bit Color FPD-Link to FPD-Link II Converter

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8 Application and Implementation
DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DS90UR907Q and DS90UR908Q chipset is intended for interface between a host (graphics processor) and
a Display. It supports an 24-bit color depth (RGB888) and up to 1024 × 768 display formats. In a RGB888
application, 24 color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are
supported across the serial link with PCLK rates from 5 to 65 MHz. The chipset may also be used in 18-bit color
applications. In this application three to six general purpose signals may also be sent from host to display.
8.1.1 Power-Up Requirements and PDB Pin
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to V_DDIO, TI recommends using a 10-kΩ pullup and a
22-uF capacitor to GND to delay the PDB input signal.
8.1.2 Transmission Media
The DS90UR907Q and the companion deserializer chipset is intended to be used in a point-to-point
configuration, through a PCB trace, or through twisted pair cable. The DS90UR907Q provide internal
terminations providing a clean signaling environment. The interconnect for LVDS should present a differential
impedance of 100 Ω. Use cables and connectors that have matched differential impedance to minimize
impedance discontinuities. Shielded or unshielded cables may be used depending upon the noise environment
and application requirements.
8.1.3 Alternate Color / Data Mapping
Color Mapped data pin names are provided to specify a recommended mapping for 24-bit and 18-bit
Applications. When connecting to earlier generations of FPD-Link II deserializer devices, a color mapping review
is recommended to ensure the correct connectivity is obtained. Table 7 provides examples for interfacing
between DS90UR907Q and different deserializers.
FPD-Link
RxIN3
Bit Number
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Table 7. Alternate Color / Data Mapping
RGB (LSB
Example)
B1
B0
G1
G0
R1
R0
DS90UR906Q DS90UR124
B1
B0
G1
G0
R1
R0
DS99R124Q
N/A
DS90C124
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