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DRV8704 Datasheet, PDF (8/38 Pages) Texas Instruments – Dual H-Bridge PWM Gate Driver
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DRV8704
SLVSD29 – OCTOBER 2015
6.6 SPI Timing Requirements
over operating free-air temperature range (unless otherwise noted)
NO.
MIN
1 tCYC
2 tCLKH
3 tCLCL
4 tSU(SDATI)
5 tH(SDATI)
6 tSU(SCS)
7 tH(SCS)
8 tL(SCS)
9 tD(SDATO)
tSLEEP
tRESET
Clock cycle time
250
Clock high time
25
Clock low time
25
Setup time, SDATI to SCLK
5
Hold time, SDATI to SCLK
1
Setup time, SCS to SCLK
5
Hold time, SCS to SCLK
1
Inactive time, SCS (between writes)
100
Delay time, SCLK to SDATO (during read)
Wake time (SLEEPn inactive to high-side gate drive enabled)
Delay from power-up or RESETn high until serial interface functional
6
7
8
SCS
SCLK
SDATI
X
SDATO
1
2
3
X
45
9
Figure 1. Timing Diagram
SDATO
valid
www.ti.com
MAX
10
1
10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
μs
8
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