DRV8704 Datasheet, PDF (18/38 Pages) Texas Instruments – Dual H-Bridge PWM Gate Driver

DRV8704
SLVSD29 – OCTOBER 2015
www.ti.com
In a system with capacitor charge Q and desired rise time RT, IDRIVE, and TDRIVE can be initially selected
based on:
IDRIVE ! ^Q
RT
(2)
TDRIVE > 2 × RT
(3)
For best results, select the smallest IDRIVE and TDRIVE that meet the above conditions.
Example:
If the gate charge is 15 nC and the desired rise time is 400 ns, then select
IDRIVEP = 50 mA, IDRIVEN = 100 mA
TDRIVEP = TDRIVEN = 1050 ns
7.3.8 External FET Selection
In a typical setup, the DRV8704 can support external FETs over 50 nC each. However, this capacity can be
lower or higher based on the device operation. For an accurate calculation of FET driving capacity, use
Equation 4.
20 mA u 2 u DTIME TBLANK TOFF
Q
4
(4)
Example:
If a DTIME is set to 0 (410 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0 (525 ns), then the DRV8704
will support Q < 11.5 nC FETs. (Please note that this is an absolute worst-case scenario with a PWM
frequency about 430 kHz)
If a DTIME is set to 0 (410 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0x14 (10 µs), then the
DRV8704 will support Q < 59 nC FETs (PWM frequency about 85 kHz).
If a DTIME is set to 0 (410 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0x60 (48 µs), then the
DRV8704 will support Q < 249 nC FETs (PWM frequency about 20 kHz).
7.3.9 Protection Circuits
The DRV8704 is fully protected against undervoltage, overcurrent, and overtemperature events.
7.3.9.1 Overcurrent Protection (OCP)
Overcurrent is sensed by monitoring the voltage drop across the external FETs. If the voltage across a driven
FET exceeds the value programmed by the OCPTH bits in the DRIVE register for more than the time period
specified by the OCPDEG bits in the DRIVE register, an OCP event is recognized. During an OCP event, the H-
bridge experiencing the OCP event is disabled. In addition, the corresponding xOCP bit in the STATUS register
is set, and the FAULTn pin is driven low. The H-bridge (or H-bridges) will remain off, and the xOCP bit will
remain set, until it is written to 0, or the device is reset.
7.3.9.2 Gate Driver Fault (PDF)
If excessive current is detected on the gate drive outputs (which would be indicative of a failed/shorted output
FET or PCB fault), the H-bridge experiencing the fault is disabled, the xPDF bit in the STATUS register is set,
and the FAULTn pin is driven low. The H-bridge will remain off, and the xPDF bit will remain set until it is written
to 0, or the device is reset.
7.3.9.3 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled, the OTS bit in the STATUS
register will be set, and the FAULTn pin will be driven low. Once the die temperature has fallen to a safe level
operation will automatically resume and the OTS bit will reset. The FAULTn pin will be released after operation
has resumed.
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