DRV8704 Datasheet, PDF (6/38 Pages) Texas Instruments – Dual H-Bridge PWM Gate Driver

DRV8704
SLVSD29 – OCTOBER 2015
6.5 Electrical Characteristics
T_A = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
POWER SUPPLIES (VM)
I_VM
VM operating supply current
VM = 24 V
I_VMQ
VM sleep mode supply current VM = 24 V, SLEEPn low
INTERNAL LINEAR REGULATORS (V5, VINT)
V5
V5 output voltage
VM ≥ 12 V, IOUT ≤ 10 mA
4.8
VINT
VINT voltage
No external load; reference only
1.7
LOGIC-LEVEL INPUTS (SLEEPn, AIN1, AIN2, BIN1, BIN2, RESET, SCLK, SDATI, SCS)
V_IL
Input logic low voltage
V_IH
Input logic high voltage
1.5
V_HYS
Input logic hysteresis
I_IL
Input logic low current
V_IN = 0 V
–5
I_IH
Input logic high current
V_IN = 5 V
24
OPEN DRAIN OUTPUTS (nFAULT, SDATO)
V_OL
Output logic low voltage
I_O = 5 mA
I_OH
Output logic high leakage
10kΩ pullup to 3.3 V
–1
GATE DRIVERS
V_OUTH
High-side gate drive output
voltage
VM = 24 V, I_O = 100 μA
V_OUTL
Low-side gate drive output
voltage
VM = 24 V, I_O = 100 μA
t_DEAD
Output dead time digital delay
(dead time is enforced in analog
circuits)
DTIME = 00
DTIME = 01
DTIME = 10
DTIME = 11
IDRIVEP = 00
I_OUT,SRC
Peak output sourcing gate drive ^{IDRIVEP = 01}
current
IDRIVEP = 10
IDRIVEP = 11
IDRIVEN = 00
I_OUT,SNK
Peak output sinking gate drive
current
IDRIVEN = 01
IDRIVEN = 10
IDRIVEN = 11
TDRIVEP = 00
t_DRIVE,SRC
Peak current drive time for
sourcing
TDRIVEP = 01
TDRIVEP = 10
TDRIVEP = 11
TDRIVEN = 00
t_DRIVE,SNK
Peak current drive time for
sinking
TDRIVEN = 01
TDRIVEN = 10
TDRIVEN = 11
CURRENT REGULATION
t_OFF
PWM off time adjustment range Set by TOFF register
0.53
t_BLANK
Current sense blanking time
Set by TBLANK register
1.05
ISGAIN = 00
ISGAIN = 01
A_V
Current sense amplifier gain
ISGAIN = 10
ISGAIN = 11
TYP
17
65
5
1.8
300
50
VM + 10
10
410
460
670
880
50
100
150
200
100
150
200
400
263
525
1050
2100
263
525
1050
2100
5
10
20
40
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MAX UNIT
22 mA
98 μA
5.2 V
1.9 V
0.8 V
V
mV
5 μA
70 μA
0.5 V
1 μA
V
V
ns
mA
mA
ns
ns
134 μs
7.0 μs
V/V
6
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