DRV8704 Datasheet, PDF (28/38 Pages) Texas Instruments – Dual H-Bridge PWM Gate Driver

DRV8704
SLVSD29 – OCTOBER 2015
10 Layout
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10.1 Layout Guidelines
The VM terminal should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended
value of 0.01 μF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick
trace or ground plane connection to the device GND pin.
The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component may be an
electrolytic. The bulk capacitor should be placed to minimize the distance of the high-current path through the
external FETs. The connecting metal trace widths should be as wide as possible, and numerous vias should be
used when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver
high current.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.1 μF rated for VM
is recommended. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 1 μF rated for 16 V is
recommended. Place this component as close to the pins as possible.
Bypass VINT to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin
as possible.
Bypass V5 to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin as
possible.
If desired, align the external NMOS FETs as shown on the next page to facilitate layout. Route the AOUT1,
AOUT2, BOUT1, and BOUT2 nets to the motor windings.
Use separate traces to connect the xISENP and xISENN pins to the sense resistor terminals.
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