 English |
|
|
|
|
|
|
|
| DRV8704 Datasheet, PDF (15/38 Pages) Texas Instruments – Dual H-Bridge PWM Gate Driver | |||
| |||
| ◁ |
www.ti.com
I below Itrip
after tBLANK
Itrip
tON
tBLANK
tOFF
tON
tBLANK
DRV8704
SLVSD29 â OCTOBER 2015
tOFF
I above Itrip
after tBLANK
Itrip
I < Itrip
tON
tBLANK
At Itrip and after tBLANK,
slow decay
tBLANK
tOFF
tON
tBLANK
tBLANK
tOFF
I > Itrip, start
fast decay
When I < Itrip in fast decay and
tBLANK expires, change to slow
decay
Figure 11. Auto Mixed Decay
On
Fast
Decay
Slow
Decay
To accurately detect zero current, an internal offset has been intentionally placed in the zero current detection
circuit. If an external filter is placed on the current sense resistor to the xISENN and xISENP pins, symmetry
must be maintained. This means that any resistance between the bottom of the RISENSE resistor and xISENN
must be matched by the same resistor value (1% tolerance) between the top of the RISENSE resistor and xISENP.
Ensure a maximum resistance of 500 â¦. The capacitor value should be chosen such that the RC time constant is
between 50 and 60 ns. Any external filtering on these pins is optional and not required for operation.
VM
x1HS
PWM
logic
Gate
Drive
and
OCP
xOUT1
x1LS
VM
x2HS
Gate
Drive
and
OCP
xOUT2
x2LS
Comp
Comp
ISEN
amp
xISENP
CR
xISENN
RISENSE
R
Optional Filtering
Figure 12. Optional Filtering for Sense Amplifiers
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: DRV8704
Submit Documentation Feedback
15
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese