DRV8704 Datasheet, PDF (16/38 Pages) Texas Instruments – Dual H-Bridge PWM Gate Driver

DRV8704
SLVSD29 – OCTOBER 2015
www.ti.com
7.3.5 Blanking Time
After the current is enabled in an H-bridge, the voltage on the ISEN pin is ignored for a period of time before
enabling the current sense circuitry. This blanking time is adjustable from 500 ns to 5.14 µs, in 20-ns increments,
by setting the TBLANK bits in the BLANK register. Note that the blanking time also sets the minimum drive time
of the PWM.
The same blanking time is applied to the fast decay period in auto mixed decay mode. The PWM will ignore any
transitions on Itrip after entering fast decay mode, until the blanking time has expired.
7.3.6 Gate Drivers
An internal charge pump circuit and pre-drivers inside the DRV8704 directly drive N-channel MOSFETs, which
drive the motor current.
The peak drive current of the pre-drivers is adjustable by setting the bits in the DRIVE register. Peak source
currents may be set to 50 mA, 100 mA, 150 mA, or 200 mA. The peak sink current is approximately 2× the peak
source current. Adjusting the peak current will change the output slew rate, which also depends on the FET input
capacitance and gate charge.
When changing the state of the output, the peak current is applied for a short period of time (t_DRIVE), to charge
the gate capacitance. After this time, a weak current source is used to keep the gate at the desired state. When
selecting the gate drive strength for a given external FET, the selected current must be high enough to fully
charge and discharge the gate during the time when driven at full current, or excessive power will be dissipated
in the FET.
During high-side turn-on, the low-side gate is pulled low. This prevents the gate-drain capacitance of the low-side
FET from inducing turn-on.
The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time. Additional dead time is added with digital delays. This delay
can be selected by setting the DTIME bits in the CTRL register.
t_DRIVE
HS drive
(mA)
xHS
(V)
High Z
Low
Z
High Z
Low Z
High Z
t_DRIVE
High Z Low Z
LS drive
(mA)
xLS
(V)
High Z
High Z
Low
Z
t_DEAD
Figure 13. Gate Driver
16
Submit Documentation Feedback
Product Folder Links: DRV8704
t_DEAD
Copyright © 2015, Texas Instruments Incorporated