DRV8704 Datasheet, PDF (22/38 Pages) Texas Instruments – Dual H-Bridge PWM Gate Driver

DRV8704
SLVSD29 – OCTOBER 2015
BIT
NAME
7-6
TDRIVEP
9-8
IDRIVEN
11-10
IDRIVEP
Table 10. DRIVE Register (continued)
SIZE
2
2
2
R/W
DEFAULT
DESCRIPTION
R/W
10
Gate drive source time
00: 263 ns
01: 525 ns
10: 1.05 µs
11: 2.10 µs
R/W
11
Gate drive peak sink current
00: 100-mA peak (sink)
01: 200-mA peak (sink)
10: 300-mA peak (sink)
11: 400-mA peak (sink)
R/W
11
Gate drive peak source current
00: 50-mA peak (source)
01: 100-mA peak (source)
10: 150-mA peak (source)
11: 200-mA peak (source)
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7.5.1.8 STATUS Register (Address = 0x07h)
BIT
0
1
2
3
4
5
11-6
NAME
OTS
AOCP
BOCP
APDF
BPDF
UVLO
Reserved
SIZE
1
1
1
1
1
1
5
Table 11. STATUS Register
R/W
DEFAULT
DESCRIPTION
R
0
0: Normal operation
1: Device has entered overtemperature shutdown
Write a ‘0’ to this bit to clear the fault and resume
operation
Operation automatically resumes once
temperature has fallen to safe levels
R/W
0
0: Normal operation
1: Channel A overcurrent shutdown
Write a ‘0’ to this bit to clear the fault and resume
operation
R/W
0
0: Normal operation
1: Channel B overcurrent shutdown
Write a ‘0’ to this bit to clear the fault and resume
operation
R/W
0
0: Normal operation
1: Channel A predriver fault
Write a ‘0’ to this bit to clear the fault and resume
operation
R/W
0
0: Normal operation
1: Channel B predriver fault
Write a ‘0’ to this bit to clear the fault and resume
operation
R
0
0: Normal operation
1: Undervoltage lockout
Write a ‘0’ to this bit to clear the fault and resume
operation
The UVLO bit cannot be cleared in sleep mode
Operation automatically resumes once VM has
risen
—
—
Reserved
22
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