MSP430F5229 Datasheet, PDF (75/121 Pages) Texas Instruments – MSP430F522x and MSP430F521x Mixed-Signal Microcontrollers

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MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
SLAS718E – NOVEMBER 2012 – REVISED MAY 2014
Table 6-35. Real-Time Clock Registers (Base Address: 04A0h) (continued)
RTC year low
RTC year high
RTC alarm minutes
RTC alarm hours
RTC alarm day of week
RTC alarm days
REGISTER DESCRIPTION
REGISTER
RTCYEARL
RTCYEARH
RTCAMIN
RTCAHOUR
RTCADOW
RTCADAY
OFFSET
16h
17h
18h
19h
1Ah
1Bh
Table 6-36. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
16-bit operand 1 – multiply
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
16 × 16 result low word
16 × 16 result high word
16 × 16 sum extension register
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
32 × 32 result 0 – least significant word
32 × 32 result 1
32 × 32 result 2
32 × 32 result 3 – most significant word
MPY32 control register 0
REGISTER
MPY
00h
MPYS
02h
MAC
04h
MACS
06h
OP2
08h
RESLO
0Ah
RESHI
0Ch
SUMEXT
0Eh
MPY32L
10h
MPY32H
12h
MPYS32L
14h
MPYS32H
16h
MAC32L
18h
MAC32H
1Ah
MACS32L
1Ch
MACS32H
1Eh
OP2L
20h
OP2H
22h
RES0
24h
RES1
26h
RES2
28h
RES3
2Ah
MPY32CTL0
2Ch
OFFSET
Table 6-37. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
DMA channel 0 control
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA channel 1 control
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
REGISTER
DMA0CTL
00h
DMA0SAL
02h
DMA0SAH
04h
DMA0DAL
06h
DMA0DAH
08h
DMA0SZ
0Ah
DMA1CTL
00h
DMA1SAL
02h
DMA1SAH
04h
DMA1DAL
06h
DMA1DAH
08h
OFFSET
Copyright © 2012–2014, Texas Instruments Incorporated
Short-Form Description
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