MSP430F5229 Datasheet, PDF (16/121 Pages) Texas Instruments – MSP430F522x and MSP430F521x Mixed-Signal Microcontrollers

MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
SLAS718E – NOVEMBER 2012 – REVISED MAY 2014
www.ti.com
NAME
Table 4-2. Terminal Functions (continued)
TERMINAL
RG
C
NO.
ZQ
E
YFF
RG
Z
I/O⁽¹⁾ SUPPLY
DESCRIPTION
P4.6/PM_NONE ⁽⁷⁾
47 C8 H2 35 I/O
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: no secondary function
P4.7/PM_NONE ⁽⁷⁾
48 C7 G3 N/A I/O
DVIO
General-purpose digital I/O with reconfigurable port mapping secondary function (not
available on all device types)
Default mapping: no secondary function (not available on all device types)
P7.0/TB0.0 ⁽⁷⁾
49
B8,
B9
H1 N/A
I/O
DVCC
General-purpose digital I/O (not available on all device types)
TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on all device
types)
P7.1/TB0.1 ⁽⁷⁾
50 A9 G2 N/A I/O
DVCC
General-purpose digital I/O (not available on all device types)
TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device
types)
P7.2/TB0.2 ⁽⁷⁾
51 B7 F3 N/A I/O
DVCC
General-purpose digital I/O (not available on all device types)
TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device
types)
P7.3/TB0.3 ⁽⁷⁾
52 A8 G1 N/A I/O
DVCC
General-purpose digital I/O (not available on all device types)
TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on all device
types)
P7.4/TB0.4 ⁽⁸⁾
53 A7 F2 N/A I/O
DVCC
General-purpose digital I/O (not available on all device types)
TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on all device
types)
P7.5/TB0.5 ⁽⁸⁾
BSLEN ⁽⁸⁾
RST/NMI ⁽⁸⁾
54 A6 F1 N/A I/O
55 B6 E2 36 I
56 A5 E3 37 I
DVCC
DVIO
General-purpose digital I/O (not available on all device types)
TB0 CCR5 capture: CCI5A input, compare: Out5 output (not available on all device
types)
BSL enable with internal pulldown
DVIO
Reset input active low^(9)(10)
Non-maskable interrupt input⁽⁹⁾
P5.2/XT2IN
57 B5 E1 38 I/O
DVCC
General-purpose digital I/O
Input terminal for crystal oscillator XT2⁽¹¹⁾
P5.3/XT2OUT
58 B4 D1 39 I/O
DVCC ^{General-purpose digital I/O}
Output terminal of crystal oscillator XT2
TEST/SBWTCK ⁽¹²⁾
59 A4 E4 40 I
DVCC ^{Test mode pin – Selects four wire JTAG operation}
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
PJ.0/TDO ⁽¹³⁾
60 C5 D2 41 I/O
DVCC ^{General-purpose digital I/O}
JTAG test data output port
PJ.1/TDI/TCLK ⁽¹³⁾
61 C4 C1 42 I/O
DVCC ^{General-purpose digital I/O}
JTAG test data input or test clock input
(8) This pin function is supplied by DVIO. See for input and output requirements.
(9) This pin is configurable as reset or NMI and resides on the DVIO supply domain. When driven from external, the input swing levels from
DVSS to DVIO are required.
(10) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(11) When in crystal bypass mode, XT2IN can be configured so that it can support an input digital waveform with swing levels from DVSS to
DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing.
(12) See Section 6.6 and Section 6.7 for use with BSL and JTAG functions.
(13) See Section 6.7 for use with JTAG function.
16
Terminal Configuration and Functions
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