MSP430F5229 Datasheet, PDF (43/121 Pages) Texas Instruments – MSP430F522x and MSP430F521x Mixed-Signal Microcontrollers

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MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
SLAS718E – NOVEMBER 2012 – REVISED MAY 2014
5.40 10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
AV_CC
V_(Ax)
PARAMETER
TEST CONDITIONS
V_CC
Analog supply voltage
AV_CC and DV_CC are connected together,
AV_SS and DV_SS are connected together,
V_(AVSS) = V_(DVSS) = 0 V
Analog input voltage range⁽²⁾
All ADC10_A pins: P1.0 to P1.5 and P3.6 and
P3.7 terminals
MIN TYP MAX UNIT
1.8
3.6 V
0
AV_CC V
Operating supply current into f_ADC10CLK = 5.0 MHz, ADC10ON = 1,
AVCC terminal, REF module REFON = 0, SHT0 = 0, SHT1 = 0,
and reference buffer off
ADC10DIV = 0, ADC10SREF = 00
2.2 V
3V
60 100
µA
75 110
Operating supply current into f_ADC10CLK = 5.0 MHz, ADC10ON = 1,
AVCC terminal, REF module REFON = 1, SHT0 = 0, SHT1 = 0,
3V
on, reference buffer on
ADC10DIV = 0, ADC10SREF = 01
113 150 µA
I_{ADC10_A}
Operating supply current into
AVCC terminal, REF module
off, reference buffer on
f_ADC10CLK = 5.0 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0, ADC10SREF = 10,
VEREF = 2.5 V
3V
105 140 µA
Operating supply current into
AVCC terminal, REF module
off, reference buffer off
f_ADC10CLK = 5.0 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0, ADC10SREF = 11,
VEREF = 2.5 V
3V
70 110 µA
C_I
Input capacitance
Only one terminal Ax can be selected at one
time from the pad to the ADC10_A capacitor
array including wiring and pad
2.2 V
3.5
pF
R_I
Input MUX ON resistance
AV_CC > 2 V, 0 V ≤ V_Ax ≤ AV_CC
1.8 V < AV_CC < 2 V, 0 V ≤ V_Ax ≤ AV_CC
36
kΩ
96
(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range V_R+ to V_R– for valid conversion results. The external
reference voltage requires decoupling capacitors. See ⁽⁾.
5.41 10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
f_ADC10CLK Input clock frequency
TEST CONDITIONS
For specified performance of ADC10_A linearity
parameters
V_CC
2.2 V, 3 V
MIN TYP MAX UNIT
0.45
5 5.5 MHz
f_ADC10OSC
Internal ADC10_A
oscillator ⁽¹⁾
ADC10DIV = 0, f_ADC10CLK = f_ADC10OSC
2.2 V, 3 V
4.2 4.8 5.4 MHz
t_CONVERT Conversion time
REFON = 0, Internal oscillator, 12 ADC10CLK
cycles, 10-bit mode
f_ADC10OSC = 4 MHz to 5 MHz
2.2 V, 3 V
2.4
3.0
µs
External f_ADC10CLK from ACLK, MCLK or SMCLK,
(2)
ADC10SSEL ≠ 0
t_ADC10ON
Turn on settling time of
the ADC
See ⁽³⁾
100 ns
t_Sample
Sampling time
R_S = 1000 Ω, R_I = 96 k Ω, C_I = 3.5 pF⁽⁴⁾
1.8 V
3
3.0 V
1
µs
µs
(1) The ADC10OSC is sourced directly from MODOSC inside the UCS.
(2) 12 × ADC10DIV × 1/f_ADC10CLK
(3) The condition is that the error in a conversion started after t_ADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(4) Approximately eight Tau (τ) are needed to get an error of less than ±0.5 LSB
Copyright © 2012–2014, Texas Instruments Incorporated
Specifications
43
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