MSP430F5229 Datasheet, PDF (17/121 Pages) Texas Instruments – MSP430F522x and MSP430F521x Mixed-Signal Microcontrollers

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MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
SLAS718E – NOVEMBER 2012 – REVISED MAY 2014
NAME
Table 4-2. Terminal Functions (continued)
TERMINAL
RG
C
NO.
ZQ
E
YFF
RG
Z
I/O⁽¹⁾ SUPPLY
DESCRIPTION
PJ.2/TMS ⁽¹³⁾
62 A3 D3 43 I/O
DVCC ^{General-purpose digital I/O}
JTAG test mode select
PJ.3/TCK ⁽¹³⁾
63 B3 B1 44 I/O
DVCC ^{General-purpose digital I/O}
JTAG test clock
RSTDVCC/SBWTDIO ⁽¹³⁾
64 A2 D4 45 I/O
DVCC
Reset input active low⁽¹⁴⁾
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated
P6.0/CB0/A0
1 A1 C2 46 I/O
DVCC
General-purpose digital I/O
Comparator_B input CB0
Analog input A0 – ADC (not available on all device types)
P6.1/CB1/A1
2 B2 A1 47 I/O
DVCC
General-purpose digital I/O
Comparator_B input CB1
Analog input A1 – ADC (not available on all device types)
P6.2/CB2/A2
3 B1 B2 48 I/O
DVCC
General-purpose digital I/O
Comparator_B input CB2
Analog input A2 – ADC (not available on all device types)
P6.3/CB3/A3
General-purpose digital I/O
4 C2 C3 1 I/O DVCC _{Comparator_B input CB3}
Analog input A3 – ADC (not available on all device types)
Reserved
N/A ⁽¹⁵⁾ N/A N/A
Reserved
QFN Pad
Pad N/A N/A Pad
QFN package pad. Connection to V_SS recommended.
(14) This non-configurable reset resides on the DVCC supply domain and has an internal pullup to DVCC. When driven from external, input
swing levels from DVSS to DVCC are required. This reset must be used for Spy-Bi-Wire communication and is not the same RST/NMI
reset as found on other devices in the MSP430 family. See Section 6.6 and Section 6.7 for details regarding the use of this pin.
(15) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
Copyright © 2012–2014, Texas Instruments Incorporated
Terminal Configuration and Functions
17
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