MSP430F5229 Datasheet, PDF (18/121 Pages) Texas Instruments – MSP430F522x and MSP430F521x Mixed-Signal Microcontrollers

MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
SLAS718E – NOVEMBER 2012 – REVISED MAY 2014
www.ti.com
5 Specifications
5.1 Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
Voltage applied at V_CC to V_SS
Voltage applied at V_IO to V_SS
Voltage applied to any pin (excluding VCORE and V_IO pins)⁽²⁾
Voltage applied to V_IO pins
Diode current at any device pin
-0.3 V to 4.1 V
-0.3 V to 2.2 V
-0.3 V to (V_CC + 0.3 V)
-0.3 V to (V_IO + 0.2 V)
±2 mA
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V_SS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
5.2 Handling Ratings
MIN
MAX
UNIT
T_stg
Storage temperature range⁽¹⁾
-55
150
°C
(1) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.3 Recommended Operating Conditions
Typical values are specified at V_CC = 3.3 V and T_A = 25°C (unless otherwise noted)
MIN NOM MAX UNIT
PMMCOREVx = 0
1.8
3.6 V
V_CC
Supply voltage during program execution and flash
PMMCOREVx = 0, 1
2.0
programming(AVCC = DVCC)^(1)(2)(3)
PMMCOREVx = 0, 1, 2
2.2
3.6 V
3.6 V
V_IO
V_SS
T_A
T_J
C_VCORE
C_DVCC/
C_VCORE
Supply voltage applied to DVIO referenced to V_SS(2)
Supply voltage (AVSS = DVSS)
Operating free-air temperature
Operating junction temperature
Recommended capacitor at VCORE⁽⁴⁾
Capacitor ratio of DVCC to VCORE
f_SYSTEM
Processor frequency (maximum MCLK frequency)⁽⁵⁾
(see Figure 5-3)
PMMCOREVx = 0, 1, 2, 3
I version
I version
PMMCOREVx = 0 (default
condition),
1.8 V ≤ V_CC ≤ 3.6 V
PMMCOREVx = 1,
2.0 V ≤ V_CC ≤ 3.6 V
PMMCOREVx = 2,
2.2 V ≤ V_CC ≤ 3.6 V
PMMCOREVx = 3,
2.4 V ≤ V_CC ≤ 3.6 V
2.4
3.6 V
1.62
1.98 V
0
V
-40
85 °C
-40
85 °C
470
nF
10
0
8
0
12
MHz
0
20
0
25
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) During V_CC and V_IO power up, it is required that V_IO ≥ V_CC during the ramp up phase of V_IO. During V_CC and V_IO power down, it is
required that V_IO ≥ V_CC during the ramp down phase of V_IO (see Figure 5-1).
(3) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.27 threshold parameters for
the exact values and further details.
(4) A capacitor tolerance of ±20% or better is required.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
18
Specifications
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