MSP430F5229 Datasheet, PDF (13/121 Pages) Texas Instruments – MSP430F522x and MSP430F521x Mixed-Signal Microcontrollers

www.ti.com
MSP430F5229, MSP430F5227, MSP430F5224, MSP430F5222
MSP430F5219, MSP430F5217, MSP430F5214, MSP430F5212
SLAS718E – NOVEMBER 2012 – REVISED MAY 2014
4.7 Signal Descriptions
NAME
Table 4-2. Terminal Functions
TERMINAL
RG
C
NO.
ZQ
E
YFF
RG
Z
I/O⁽¹⁾ SUPPLY
DESCRIPTION
P6.4/CB4/A4
General-purpose digital I/O
5 C1 A2 2 I/O DVCC _{Comparator_B input CB4}
Analog input A4 – ADC (not available on all device types)
P6.5/CB5/A5
General-purpose digital I/O
6 D2 B3 3 I/O DVCC _{Comparator_B input CB5}
Analog input A5 – ADC (not available on all device types)
P6.6/CB6/A6
7 D1 C4 N/A I/O
DVCC
General-purpose digital I/O (not available on all device types)
Comparator_B input CB6 (not available on all device types)
Analog input A6 – ADC (not available on all device types)
P6.7/CB7/A7
8 D3 A3 N/A I/O
DVCC
General-purpose digital I/O (not available on all device types)
Comparator_B input CB7 (not available on all device types)
Analog input A7 – ADC (not available on all device types)
P5.0/A8/VeREF+
General-purpose digital I/O
9 E1 B4 4 I/O DVCC _{Analog input A8 – ADC (not available on all device types)}
Input for an external reference voltage to the ADC (not available on all device types)
P5.1/A9/VeREF-
AVCC
General-purpose digital I/O
10 E2 A4 5 I/O DVCC Analog input A9 – ADC (not available on all device types)
11 F2 B5 6
Negative terminal for the ADC's reference voltage for an external applied reference
voltage (not available on all device types)
Analog power supply
P5.4/XIN
12 F1 A5 7 I/O DVCC ^{General-purpose digital I/O}
Input terminal for crystal oscillator XT1⁽²⁾
P5.5/XOUT
AVSS
DVCC
DVSS
VCORE ⁽³⁾
13 G1 A6 8 I/O
14 G2 B6 9
15 H1 A7 10
16 J1 A8 11
17 J2 B8 12
DVCC ^{General-purpose digital I/O}
Output terminal of crystal oscillator XT1
Analog ground supply
Digital power supply
Digital ground supply
DVCC _{Regulated core power supply output (internal use only, no external current loading)}
P1.0/TA0CLK/ACLK
18 H2 B7 13 I/O
DVCC
General-purpose digital I/O with port interrupt
TA0 clock signal TA0CLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0
19 H3 C7 14 I/O
DVCC
General-purpose digital I/O with port interrupt
TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
(1) I = input, O = output, N/A = not available
(2) When in crystal bypass mode, XIN can be configured so that it can support an input digital waveform with swing levels from DVSS to
DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing.
(3) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, C_VCORE.
Copyright © 2012–2014, Texas Instruments Incorporated
Terminal Configuration and Functions
13
Submit Documentation Feedback
Product Folder Links: MSP430F5229 MSP430F5227 MSP430F5224 MSP430F5222 MSP430F5219 MSP430F5217
MSP430F5214 MSP430F5212