AMC7834 Datasheet, PDF (64/93 Pages) Texas Instruments – AMC7834 12-Bit Integrated Power-Amplifier Monitor and Control System with Temperature, Current and Voltage Supervision Capabilities

AMC7834
SLAS972B – NOVEMBER 2014 – REVISED MARCH 2016
7.6.4.5 ALARMOUT Configuration Register (address = 0x1B) [reset = 0x0000]
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Figure 81. ALARMOUT Configuration Register (R/W)
15
ALARM-
LATCH-DIS
R/W-0
14
ALARMOUT-
POLARITY
R/W-0
13
ADCINT/CS-
SELECT
R/W-0
12
DAC34LOOP-
ALARMEN
R/W-0
11
DAC12LOOP-
ALARMEN
R/W-0
10
AVSS-
ALARMEN
R/W-0
9
RT2-HIGH-
ALARMEN
R/W-0
8
RT2-LOW-
ALARMEN
R/W-0
7
RT1-HIGH-
ALARMEN
R/W-0
6
RT1-LOW-
ALARMEN
R/W-0
5
LT-HIGH-
ALARMEN
R/W-0
4
LT-LOW-
ALARMEN
R/W-0
3
ADCINT4/CS4-
ALARMEN
R/W-0
2
ADCINT3/CS3-
ALARMEN
R/W-0
1
ADCINT2/CS2-
ALARMEN
R/W-0
0
ADCINT1/CS1-
ALARMEN
R/W-0
Table 28. ALARMOUT Configuration Field Descriptions
Bit Field
15
ALARM-LATCH-DIS
14
ALARMOUT-POLARITY
13
ADCINT/CS-SELECT
12
DAC34LOOP-ALARMEN
11
DAC12LOOP-ALARMEN
10
AVSS-ALARMEN
9
RT2-HIGH-ALARMEN
8
RT2-LOW-ALARMEN
7
RT1-HIGH-ALARMEN
6
RT1-LOW-ALARMEN
5
LT-HIGH-ALARMEN
4
LT-LOW-ALARMEN
3
ADCINT4/CS4-ALARMEN
2
ADCINT3/CS3-ALARMEN
1
ADCINT2/CS2-ALARMEN
0
ADCINT1/CS1-ALARMEN
Type
R/W
Reset
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Alarm latch disable bit.
When cleared to 0 the alarm bits are latched. When an alarm
occurs, the corresponding alarm bit is set to 1. The alarm bit
remains until the error condition subsides and the alarm register
is read. Before reading, the alarm bit is not cleared even if the
alarm condition disappears.
When set to 1 the alarm bits are not latched. When the alarm
condition subsides, the alarm bits are cleared regardless of
whether the alarm bits have been read or not.
ALARMOUT polarity bit.
When cleared to 0 the ALARMOUT pin is active low.
When set to 1 the ALARMOUT pin is active high.
When cleared to 0 the threshold values in registers 0x40 to 0x47
apply to ADC inputs ADCINT[1–4]. This setting should be used
for closed-loop mode operation.
When set to 1 the threshold values in registers 0x40 to 0x47
apply to current sense measurements CS[1–4]. This setting
should be used for open-loop mode operation.
These bits select the alarm events that trigger the ALARMOUT
pin.
When set to 1 an alarm event associated with the corresponding
bit will trigger the ALARMOUT pin.
When cleared to 0 an alarm event associated with the
corresponding bit does not affect the ALARMOUT pin.
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