AMC7834 Datasheet, PDF (6/93 Pages) Texas Instruments – AMC7834 12-Bit Integrated Power-Amplifier Monitor and Control System with Temperature, Current and Voltage Supervision Capabilities

AMC7834
SLAS972B – NOVEMBER 2014 – REVISED MARCH 2016
www.ti.com
PIN
NAME
NO.
IOV_DD
12
PAV_DD
41
PA_ON
40
REF_CMP
42
REF_IN
20
REF_OUT
21
RESET
5
SCLK
7
SDI
9
SDO
10
SENSE1+
39
SENSE1–
38
SENSE2+
37
SENSE2–
36
SENSE3+
34
SENSE3–
33
SENSE4+
32
SENSE4–
31
SLEEP1
3
SLEEP2
4
VCLAMP1
30
VCLAMP2
29
Thermal Pad
Pin Functions (continued)
TYPE
DESCRIPTION
—
IO supply voltage (1.7 V to 3.6 V). This pin sets the I/O operating voltage and threshold
levels.
— Power supply for the PA_ON control signal (4 V to 20 V).
PA_ON is a synchronization signal capable of driving an external PMOS switch and
controlling the flow of drain current to a power amplifier (PA) transistor. The PA_ON pin has
an internal 120 kΩ pull-up resistor to the PAV_DD pin. The maximum output voltage is set by
O
the PAV_DD pin and limited to 20 V. For drain voltages higher than 20 V, tying the PAV_DD pin
to the AV_DD pins and scaling the control signal externally is recommended. The PA_ON
signal state can be set through a register write but it can also be configured to trigger
automatically in the case of an ALARM event or when any of the SLEEP signals is
activated.
I/O
Reference compensation capacitor connection. Connect a 4.7 μF capacitor between this
pin and the AGND4 pin for ADC reference compensation.
I
Reference input to the device. This pin can be connected to the REF_OUT pin to use the
device internal reference or alternatively to an external voltage reference source.
Internal voltage reference output. Connect this pin directly to the REF_IN pin to operate the
O device in internal reference mode. An external buffer amplifier with a high impedance input
is required to drive an external load. This pin can be left unconnected.
I
Active low reset input. Logic low on this pin causes the device to perform a hardware reset.
I
Serial interface clock.
I
Serial interface data input. Data is clocked into the input shift register on each rising edge
of the SCLK pin.
O
Serial interface data output. The SDO pin is in high impedance when the CS pin is high.
Data is clocked out of the input shift register on each falling edge of the SCLK pin.
I
Current sense 1 external sense resistor power connection
I
Current sense 1 external sense resistor load connection
I
Current sense 2 external sense resistor power connection
I
Current sense 2 external sense resistor load connection
I
Current sense 3 external sense resistor power connection
I
Current sense 3 external sense resistor load connection
I
Current sense 4 external sense resistor power connection
I
Current sense 4 external sense resistor load connection
I
Active high asynchronous power down digital input 1. The power down functions of this pin
are register configurable.
I
Active high asynchronous power down digital input 2. The power down functions of this pin
are register configurable.
Power-on reset and clamp voltage control input for bipolar DACs 1 and 2. The resulting
I
power-on reset (POR) and clamp voltage value is given by Equation 1.
CLAMP = –3 × VCLAMP[1:2]
(1)
I
Power-on reset and clamp voltage control input for bipolar DACs 3 and 4. The resulting
POR and clamp voltage value is given by Equation 1.
The thermal pad is located on the bottom-side of the device package. The thermal pad
— should be tied to the same potential as the AV_SS pin for optimal thermal dissipation.
Alternatively, the thermal pad can be left unconnected.
6
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