AMC7834 Datasheet, PDF (29/93 Pages) Texas Instruments – AMC7834 12-Bit Integrated Power-Amplifier Monitor and Control System with Temperature, Current and Voltage Supervision Capabilities

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AMC7834
SLAS972B – NOVEMBER 2014 – REVISED MARCH 2016
Data written to the DAC data registers is initially stored in the DAC buffer registers. The transfer of data from the
DAC buffer registers to the active registers can be set to occur immediately (asynchronous mode) or initiated by
a DAC trigger signal (synchronous mode). When the active registers are updated, the DAC outputs change to the
new values. When the host reads from a DAC data register, the value held in the DAC active register is returned
(not the value held in the buffer register).
The update mode of the DACs is determined by the DAC sync register (address 0x15). In asynchronous mode, a
write to a DAC data register results in an immediate update of the DAC active register and the corresponding
output. In synchronous mode, writing to a DAC data register does not automatically update the DAC output.
Instead, the update occurs only after a DAC trigger event. A DAC trigger is generated either through the DAC-
TRIG bit in the DAC and ADC trigger register (address 0x1C) or by the DACTRIG pin. By setting the
synchronization properly, several DACs can be updated simultaneously.
7.3.1.3 DAC Clamp Operation
Each DAC can be set to a clamp mode using either hardware or software. When a DAC goes to clamp mode,
the DAC output is immediately set to the corresponding clamp voltage. However, clamping does not clear the
DAC buffer or active registers making it possible to return to the same voltage being output before the clamp
event was issued. The DAC data registers can be updated while the DACs are in clamp mode allowing the DACs
to output new values upon return to normal operation. When the DACs exit clamp mode, the DACs are
immediately loaded with the data in the DAC active registers and the output is set back to the corresponding
level to restore operation regardless of the DAC synchronization setting.
The clamp voltage is dependent on the DAC output:
• DAC1 and DAC2: Clamp voltage is set by the voltage at pin VCLAMP1 and is equal to –3 × VCLAMP1 during
normal operation. In the special AV_SS clamp mode the clamp voltage for DAC1 and DAC2 is fixed to AV_SS.
• DAC3 and DAC4: Clamp voltage is set by the voltage at pin VCLAMP2 and is equal to –3 × VCLAMP2 during
normal operation. In the special AV_SS clamp mode the clamp voltage for DAC3 and DAC4 is fixed to AV_SS.
• AUXDAC1 through AUXDAC4: The clamp voltage for each of the auxiliary DACs is fixed to AGND.
The clamp register (address 0x17) allows clamping of the DACs through software. The DAC1-DAC2 pair, DAC3-
DAC4 pair, and each auxiliary DAC has a corresponding DAC clamp bit. Setting this bit to 1 forces the
corresponding DAC pair or individual auxiliary DAC to enter clamp mode. Clearing the bit to 0 restores normal
operation.
Additionally, in the unique case of the AV_DD supply falling outside its specified operating range the bipolar DACs
enter the alternative AV_SS clamp mode. With the AV_DD supply outside of the valid operating range the bipolar
DAC output buffers become inactive thus creating the potential for unexpected output voltages. The AV_SS clamp
mode prevents this condition by setting all bipolar DAC outputs to AV_SS through a resistive path.
NOTE
If the DAC or DAC pair is forced to clamp by one of the SLEEP pins, write commands to
the corresponding DAC clamp bit are ignored.
The DACs can also be forced to clamp through the SLEEP1 and SLEEP2 pins. When either pin goes high, the
corresponding DAC pair and auxiliary DAC associated with each pin are forced into clamp mode. The SLEEP1
register (address 0x18) determines which DACs are forced to clamp when the SLEEP1 pin goes high. The
register contains one bit for each DAC pair (DAC1-DAC2 and DAC3-DAC4) and each auxiliary DAC. Likewise,
the SLEEP2 register (address 0x19) determines which DACs go into clamp when the SLEEP2 pin goes high. In
addition to forcing the DACs into clamp mode, the SLEEP1 and SLEEP2 pin and registers allow control of the
PA_ON pin.
Although a high state on the SLEEP pins force the associated DACs to clamp immediately, returning to a low
state does not necessarily force the DAC to return to normal operation. If the end application requires the DACs
to exit clamp mode in a particular sequence, this sequence can be controlled by the SNOOZE bits in the
SLEEP1 and SLEEP2 registers. When a SNOOZE bit is set to 1, bringing a DAC back to normal operation
requires the SLEEP pin to return to a low state first, followed by a write to the DAC clamp register (address 0x17)
to clear the clamp condition. If the SNOOZE bit is cleared to 0, setting the SLEEP pin to a low state immediately
clears the clamp condition and returns the DAC to normal operation without the need for any register writes.
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