AMC7834 Datasheet, PDF (50/93 Pages) Texas Instruments – AMC7834 12-Bit Integrated Power-Amplifier Monitor and Control System with Temperature, Current and Voltage Supervision Capabilities

AMC7834
SLAS972B – NOVEMBER 2014 – REVISED MARCH 2016
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Based on the target drain current and required PA gain ramp rate, the Closed Loop input code step can be
divided by the slew-rate control block into smaller steps that are applied to the control loop every 200 μs. The
slew-rate for each control loop is set by the Closed Loop Settling Time register (address 0x14). Issuing multiple,
smaller code steps over time instead of one large code step helps achieve a more linear PA-gain ramp rate.
Table 8 shows the control-loop settling time as a function of the slew-rate control setting.
Table 8. Closed-Loop Settling Time
LOOPn-SET[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
All others
SETTLING TIME (ms)
0.8
1.6
2.4
3.2
4.8
6.4
9.6
12.8
19.2
25.6
28.8
Not valid
Under normal conditions the code output by the slew-rate control block equals the ADC output in steady state.
When the loop is disturbed as a result of a change on the target drain current or PA characteristics, the error
between the slew-rate controller and ADC outputs is accumulated every 200 μs by the digital integrator. An
optional external RC filter at the DAC output helps to smooth out the DAC steps at the input of the PA FET gate.
The external filter time constant must be less than 50 µs.
The gain from the DAC output to the ADC input is given by Equation 11.
gm_{(PA_FET)} × R_(SENSE)
where
• gm_{(PA_FET)} is the transconductance for the PA FET
(11)
This value should be less than 0.8 to ensure stability of the control loop.
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