AMC7834 Datasheet, PDF (27/93 Pages) Texas Instruments – AMC7834 12-Bit Integrated Power-Amplifier Monitor and Control System with Temperature, Current and Voltage Supervision Capabilities

www.ti.com
AMC7834
SLAS972B – NOVEMBER 2014 – REVISED MARCH 2016
Feature Description (continued)
7.3.1.1 DAC Configuration
The eight DACs are split into bipolar and auxiliary outputs based on their output range and clamping capabilities
as listed in Table 1. After power-on or a reset event the DAC outputs are directed automatically to the
corresponding clamp value and all DAC buffer and active registers are set to the default values.
DAC
DAC1 and DAC2
DAC3 and DAC4
AUXDAC1
AUXDAC2
AUXDAC3
AUXDAC4
TYPE
Bipolar
Auxiliary
Table 1. DAC Group Configuration
OUTPUT RANGES CLAMP VOLTAGE
0 to 5 V
–4 to 1 V
–5 to 0 V
–3 × VCLAMP1 or
AV_SS
–3 × VCLAMP2 or
AV_SS
POWER SUPPLY
RANGE
AV_SS to AV_DD
0 to 5 V
2.5 to 7.5 V
AGND
AGND to AV_CC
CLOSED LOOP
OPERATION
CAPABLE?
Yes
No
7.3.1.1.1 Bipolar DACs (DAC1, DAC2, DAC3, and DAC4)
The bipolar DACs are configured as DAC pairs (DAC1-DAC2 and DAC3-DAC4). The output range for each
bipolar DAC pair can be configured through the DAC Range register (address 0x16) to one of the following: 0 to
5 V, –5 to 0 V, or –4 to 1 V. The POR and clamp value of each DAC pair is set by the pins VCLAMP1 (for the
DAC1-DAC2 pair) and VCLAMP2 (for the DAC3-DAC4 pair) to any voltage between AV_SS and 0 V during normal
operation. If AV_DD falls outside the device specified operating range the bipolar DACs enter the special AV_SS
clamp mode and their outputs are set to AV_SS. The full-scale output range of the bipolar DACs is limited by the
power supplies, AV_DD and AV_SS.
The bipolar DACs operate as standalone DACs when the AMC7834 is set in open-loop mode (LOOP-EN bit set
to 0 in register 0x10). Figure 45 shows a high level block diagram of each bipolar DAC when operating in open-
loop mode.
AVDD
WRITE
Serial Interface
DAC Data Register
READ
DAC
Buffer Register
DAC
0
Active Register
DAC Trigger
(synchronous mode)
0x000
1
(asynchronous mode)
Resistor String
CLAMP MODE
DAC
Output
Configuration
VOUT
DAC output
AVSS CLAMP MODE
VCLAMP[1,2]
AVSS
Figure 45. Bipolar DAC Block Diagram — Open Loop Operation
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: AMC7834
Submit Documentation Feedback
27