AMC7834 Datasheet, PDF (13/93 Pages) Texas Instruments – AMC7834 12-Bit Integrated Power-Amplifier Monitor and Control System with Temperature, Current and Voltage Supervision Capabilities

www.ti.com
AMC7834
SLAS972B – NOVEMBER 2014 – REVISED MARCH 2016
Electrical Characteristics—General Specifications (continued)
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. AV_DD = DV_DD = 5 V, AV_CC = 5 V, AV_SS = –5 V, IOV_DD = 1.8 to 3.3 V, PAV_DD = 5 V, AGND = DGND =
0 V, external 2.5 V reference, DAC output range = 0 to 5 V for all DACs, no load on the DACs, current sense inputs common
mode at 48 V, T_A = –40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER REQUIREMENTS
I_AVDD
I_AVCC
I_AVSS
I_DVDD
I_IOVDD
I_PAVDD
AV_DD supply current
AV_CC supply current
AV_SS supply current
DV_DD supply current
IOV_DD supply current
PAV_DD supply current
Power consumption
POWER-MODE = 10.
AV_DD = DV_DD = 5.5 V, AV_CC = 5.5 V
PAV_DD = 20 V, AV_SS = –5.5 V, IOV_DD = 3.6 V
All monitoring channels enabled
Bipolar DACs in –5 to 0 V range
Auxiliary DACs in 0 to 5 V range
All DACs at 800h code. PA_ON in "ON" state
10
12.5 mA
1.5
2 mA
–3.5
–2.5
mA
2.5
3 mA
1.75
2.5
µA
170
250
µA
95
120.5 mW
I_AVDD
I_AVCC
I_AVSS
I_DVDD
I_IOVDD
I_PAVDD
AV_DD supply current
AV_CC supply current
AV_SS supply current
DV_DD supply current
IOV_DD supply current
PAV_DD supply current
Power consumption
POWER-MODE = 00.
AV_DD = DV_DD = 5.5 V, AV_CC = 5.5 V
PAV_DD = 20 V, AV_SS = –5.5 V, IOV_DD = 3.6 V
All DACs in clamp mode at 0 V
PA_ON in "OFF" state
3.5
mA
0.2
mA
–2
mA
2.5
mA
1.75
µA
12
µA
45
mW
6.8 Serial Interface Timing Requirements⁽¹⁾⁽²⁾
AV_DD = DV_DD = 5 V, AV_CC = 5 V, AV_SS = –5 V, PAV_DD = 5 V, AGND = DGND = 0 V, external 2.5 V reference, DAC output
range = 0 to 5 V for all DACs, no load on the DACs, current sense inputs common mode at 48 V, T_A = –40°C to +105°C
(unless otherwise noted)
IOV_DD = 1.7 TO 2.7 V IOV_DD = 2.7 TO 3.6 V
MIN
MAX
MIN
MAX
UNIT
f_SCLK
t_p
t_PH
t_PL
t_su
t_h
t_(ODZ)
t_(OZD)
t_(OD)
t_su(CS)
t_h(CS)
t_(IAG)
SCLK frequency
SCLK period
SCLK pulse width high
SCLK pulse width low
SDI setup
SDI hold
SDO driven to tri-state
SDO tri-state to driven
SDO output delay
CS setup
CS hold
Inter-access gap
See Figure 1 and Figure 2.
See Figure 2.
See Figure 1 and Figure 2
0.2
10
0.2
15 MHz
100
66.67
ns
40
26
ns
40
26
ns
10
10
ns
10
10
ns
0
15
0
10 ns
0
20
0
15 ns
0
20
0
15 ns
5
5
ns
20
20
ns
15
15
ns
(1) Specified by design and characterization. Not tested during production.
(2) SDO loaded with 10 pF load capacitance for SDO timing specifications.
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: AMC7834
Submit Documentation Feedback
13